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68 Commits

Author SHA1 Message Date
Evan Cheng
d7c2c86239 Allow more use of iPTR in patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28790 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-06-15 00:16:37 +00:00
Evan Cheng
764811f145 Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28376 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-18 00:08:46 +00:00
Evan Cheng
6b12516f1a Typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28366 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-17 20:55:51 +00:00
Evan Cheng
2618d07765 Remove PointerType from target definition. Use abstract type MVT::iPTR to 
represent pointer type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28363 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-17 20:37:59 +00:00
Evan Cheng
44a65fa552 Allow patterns to refer to physical registers that belong to multiple 
register classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28323 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-05-16 07:05:30 +00:00
Chris Lattner
4b2362e247 Fix a typo: Instr* -> Intr* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-04-10 22:02:59 +00:00
Chris Lattner
6a160fba22 Only compute intrinsic valuetypes when in a target .td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27197 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 00:15:00 +00:00
Chris Lattner
76f8c7c4cc revert this, it breaks things. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27196 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-28 00:03:08 +00:00
Chris Lattner
8850a1bcef Add support for decoding iPTR to the right pointer type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27188 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-27 22:48:18 +00:00
Chris Lattner
2ca956f8de Make sure to initialize the TheDef field! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27078 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 20:25:01 +00:00
Chris Lattner
43fbbc36dc Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest of 
the CodeGen* implementations.

Parse the MVT::ValueType for each operand of the intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27075 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-24 19:49:31 +00:00
Evan Cheng
dcfccac13b getEnumName() missed v8i8, v4i16, and v2i32 types 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26869 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-19 07:57:34 +00:00
Evan Cheng
9073dea7c0 New vector type v2f32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26437 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-03-01 01:10:52 +00:00
Evan Cheng
aea20f50e5 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit 
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-02-20 22:34:53 +00:00
Chris Lattner
aa77d77a43 PHI and INLINEASM are now builtin instructions provided by Target.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25673 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-27 01:45:06 +00:00
Evan Cheng
51fecc80f7 * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag and 
SNDPOutFlag to DAG nodes. These properties do not belong to target specific
instructions.
* Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's
optional. Used by ret / call, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25154 91177308-0d34-0410-b5e6-96231b3b80d8
 2006-01-09 18:27:06 +00:00
Evan Cheng
2b4ea795a2 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-26 09:11:45 +00:00
Evan Cheng
7b05bd5814 * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAG 
support which is fragile.
* Fixed a number of bugs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24996 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-23 22:11:47 +00:00
Evan Cheng
bcecf33dc2 Support for read / write from explicit registers with FlagVT type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24753 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-17 01:19:28 +00:00
Evan Cheng
3aa39f439a * Added an explicit type field to ComplexPattern. 
* Renamed MatchingNodes to RootNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24636 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 02:14:08 +00:00
Evan Cheng
0fc7198890 Added support for ComplexPattern. These are patterns that require C++ pattern 
matching code that is not currently auto-generated by tblgen, e.g. X86
addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24634 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-08 02:00:36 +00:00
Evan Cheng
1c3d19eb15 * Commit the fix (by Chris) for a tblgen type inferencing bug. 
* Enhanced tblgen to handle instructions which have chain operand and writes a
chain result.
* Enhanced tblgen to handle instructions which produces no results. Part of
the change is a temporary hack which relies on instruction property (e.g.
isReturn, isBranch). The proper fix would be to change the .td syntax to
separate results dag from ops dag.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24587 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-04 08:18:16 +00:00
Nate Begeman
6510b22cec Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 04:51:06 +00:00
Nate Begeman
86193d1190 Nuke CodeGenInstruction's ValueType member, it is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24556 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-12-01 00:12:04 +00:00
Nate Begeman
02fc8ff800 Add the new vector types to tablegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24514 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-29 06:19:38 +00:00
Chris Lattner
3367079b0b Initialize this variable on all paths, fixing a crasher in windows. Thanks 
to JeffC for pointing this out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24426 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-19 07:48:33 +00:00
Chris Lattner
65303d6bd7 Teach tblgen about instruction operands that have multiple MachineInstr 
operands, digging into them to find register values (used on X86).  Patch
by Evan Cheng!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-11-19 07:05:57 +00:00
Chris Lattner
b0e103d46b Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accurately 
reflect what it is.
Convert some more code over to use it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24072 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-28 22:49:02 +00:00
Chris Lattner
75ee2eb4e2 Do not let getLegalValueTypes return a list with duplicates in it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23723 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-10-14 03:54:49 +00:00
Chris Lattner
c4a8b73ab3 force all instruction operands to be named. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23358 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-14 21:13:50 +00:00
Chris Lattner
5d7d3dba9c Check that operands have unique names. REJECT instructions with broken operand 
lists: only don't parse them if they are entirely missing (sparcv9).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23355 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-14 21:05:02 +00:00
Chris Lattner
8f493130bb Add a new Record::getValueAsCode method to mirror the other getValueAs* 
methods.  Use it to simplify some code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23336 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-13 21:44:28 +00:00
Chris Lattner
e9f4ba8dd4 Compute the value types that are natively supported by a target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23282 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-09-08 21:43:21 +00:00
Chris Lattner
e3cbf823f0 spell this right 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23099 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 20:55:40 +00:00
Chris Lattner
5f89bf0f9d spell this variable right 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23095 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 20:42:52 +00:00
Chris Lattner
8b50f9b8dc Expose a new flag to TargetInstrInfo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23094 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-26 20:40:46 +00:00
Chris Lattner
ac46893e24 Split register class "Methods" into MethodProtos and MethodBodies 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22928 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 19:12:51 +00:00
Chris Lattner
c67c18fd23 Read the namespace field from register classes 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22918 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 18:45:20 +00:00
Chris Lattner
bfd4f55202 Fix a problem jeffc noticed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22903 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-19 06:16:04 +00:00
Chris Lattner
cfbf96aa9c Figure out how many operands each instruction has, keep track of whether 
or not it's variable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22885 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-08-18 23:38:41 +00:00
Misha Brukman
3da94aec4d Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-04-22 00:00:37 +00:00
Chris Lattner
d648867173 Refactor code for numbering instructions into CodeGenTarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19758 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-22 18:58:51 +00:00
Chris Lattner
aad75aa1a2 Expose isConvertibleToThreeAddress and isCommutable bits to the code generator. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19243 91177308-0d34-0410-b5e6-96231b3b80d8
 2005-01-02 02:29:04 +00:00
Misha Brukman
35e83cc970 * Add option to read isLittleEndianEncoding for InstrInfo classes 
* Doxygen-ify some function comments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16974 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-14 05:50:43 +00:00
Chris Lattner
560a79f1ea Add initial support for variants. This just parses the new format, no 
functionality is added


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16636 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-10-03 19:34:31 +00:00
Nate Begeman
cdd66b524f Add support for the isLoad and isStore flags, needed by the instruction scheduler 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-28 21:01:45 +00:00
Chris Lattner
5b71d3af35 Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16553 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-09-28 18:38:01 +00:00
Chris Lattner
037d732e09 Alignment is now in bits. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15976 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 20:15:25 +00:00
Chris Lattner
98df506e71 Make alignment be in bits, just like size is 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15969 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 20:00:36 +00:00
Chris Lattner
5767775505 Support "Methods" in register classes in CodgeGenRegisterClass 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15965 91177308-0d34-0410-b5e6-96231b3b80d8
 2004-08-21 19:21:21 +00:00