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Author SHA1 Message Date
Jim Grosbach
0b44aea7b5 Use tPseudoExpand for tTAILJMPrND and tTAILJMPr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134734 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:39:19 +00:00
Jim Grosbach
af7f2d6b67 Use tPseudoExpand for tTAILJMPd and tTAILJMPdND. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134732 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:32:21 +00:00
Benjamin Kramer
70629abe31 Silence compiler warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134730 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:18:13 +00:00
Jim Grosbach
8dc41f33f7 Add more info to FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134729 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:18:11 +00:00
Jim Grosbach
e36e21e830 Move Thumb tail call pseudos to Thumb.td file. 
Fix a FIXME.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134727 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:13:35 +00:00
Eli Friedman
6043548bfe Fix dangling pointer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134725 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:07:05 +00:00
Evan Cheng
480cee5d43 TargetAsmParser doesn't need reference to Target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134721 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 19:33:14 +00:00
Benjamin Kramer
11b4c952a6 Remove unused copy of UpdateInlinedAtInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134720 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 19:32:06 +00:00
Jim Grosbach
245f5e8e2a Use ARMPseudoExpand for ARM tail calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134719 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 18:50:22 +00:00
Jim Grosbach
9ca2a778b6 Shuffle productions around a bit. 
No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 18:26:27 +00:00
Jim Grosbach
4559a7bcfd Use ARMPseudoExpand for BLr9, BLr9_pred, BXr9, and BXr9_pred. 
TableGen'erated MC lowering pseudo-expansion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134712 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 18:15:12 +00:00
Evan Cheng
fbc38d2c16 Fix a dangling reference. Patch by Dave Abrahams. pr10311 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134709 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 18:04:22 +00:00
Devang Patel
2cf158ec4b Refactor. It is inliner's responsibility to update line number information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 18:01:31 +00:00
Chandler Carruth
549a85138c Add CMake support for the new TableGen file introduced in r134705. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 17:54:08 +00:00
Jim Grosbach
53e3fc463e Use TableGen'erated pseudo lowering for ARM. 
Hook up the TableGen lowering for simple pseudo instructions for ARM and
use it for a subset of the many pseudos the backend has as proof of concept.

More conversions to come.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 17:40:42 +00:00
Jim Grosbach
86f9adb8be TableGen'erated MC lowering for simple pseudo-instructions. 
This allows the (many) pseudo-instructions we have that map onto a single
real instruction to have their expansion during MC lowering handled
automatically instead of the current cumbersome manual expansion required.
These sorts of pseudos are common when an instruction is used in situations
that require different MachineInstr flags (isTerminator, isBranch, et. al.)
than the generic instruction description has. For example, using a move
to the PC to implement a branch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134704 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 17:36:35 +00:00
Devang Patel
90b40414a0 Refactor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134703 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 17:09:57 +00:00
Devang Patel
80efd4e96b Make provision to have floating point constants in .debug_loc expressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134702 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 16:49:43 +00:00
Benjamin Kramer
3492a4af12 Apparently we can't expect a BinaryOperator here. 
Should fix llvm-gcc selfhost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 12:08:24 +00:00
NAKAMURA Takumi
4455397122 cmake/modules/LLVMLibDeps.cmake: Update to appease cmake builds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134696 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 10:45:15 +00:00
Benjamin Kramer
9c64030445 Emit a more efficient magic number multiplication for exact sdivs. 
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.

  struct foo { char x[24]; };
  long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  sarl	$3, %eax
  imull	$-1431655765, %eax, %eax
instead of
  movl	4(%esp), %eax
  subl	8(%esp), %eax
  movl	$715827883, %ecx
  imull	%ecx
  movl	%edx, %eax
  shrl	$31, %eax
  sarl	$2, %edx
  addl	%eax, %edx
  movl	%edx, %eax

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134695 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 10:31:30 +00:00
Evan Cheng
ebdeeab812 Eliminate asm parser's dependency on TargetMachine: 
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 01:53:10 +00:00
Lang Hames
1fb0955cab Make GVN look through extractvalues for recognised intrinsics. GVN can then CSE ops that match values produced by the intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134677 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 01:50:54 +00:00
Akira Hatanaka
0184336195 Raise assertion when MachineOperand has unexpected target flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134671 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 00:42:35 +00:00
Akira Hatanaka
18dfcb8a28 Make sure variable Kind is assigned a value to suppress warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134668 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 00:26:25 +00:00
Jakob Stoklund Olesen
2aa6b4c142 Fix more register allocation sensitive tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134667 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 00:24:06 +00:00
Jakob Stoklund Olesen
caab27963b Remove a test that no longer makes sense. 
It was testing a linear scan feature:

  Test if linearscan is unfavoring registers for allocation to allow
  more reuse of reloads from stack slots.

The greedy register allocator doesn't access any stack slots in this
function, so the linear scan feature was not being tested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134666 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 00:24:03 +00:00
Nick Lewycky
9bf45d0b1a Let the inline asm 'q' constraint match float, and on 64-bit double too. 
Fixes PR9602!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 00:19:27 +00:00
Eric Christopher
77ed1353bf Go ahead and emit the barrier on x86-64 even without sse2. The 
processor supports it just fine.

Fixes PR9675 and rdar://9740801


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134664 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 00:04:56 +00:00
Akira Hatanaka
794bf17cbe Lower MachineInstr to MC Inst and print to .s files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134661 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 23:56:50 +00:00
Chandler Carruth
b2760f82b1 Fix CMake build's library dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134658 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 23:45:45 +00:00
Eric Christopher
d8cca66bb4 Handle fpcr register. 
Part of PR10299 and rdar://9740322

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134653 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 22:54:12 +00:00
Eric Christopher
31b5f00c4e Add support for the X86 'l' constraint. 
Fixes PR10149 and rdar://9738585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134648 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 22:29:07 +00:00
Eric Christopher
09ad0b6894 Remove a FIXME. All of the standard ones are in the list. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134647 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 22:29:03 +00:00
Akira Hatanaka
78d62b2c7f Remove unnecessary newline. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134645 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 22:06:18 +00:00
Devang Patel
476df5f64f Add DEBUG message. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134643 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 21:44:42 +00:00
Evan Cheng
18fb1d35db Add Mode64Bit feature and sink it down to MC layer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 21:06:52 +00:00
Bill Wendling
4ae970b393 Move a function out-of-line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 21:05:13 +00:00
Akira Hatanaka
03236be44a Rather than having printMemOperand change the way memory operands are printed 
based on a modifier, split it into two functions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134637 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 20:54:20 +00:00
Akira Hatanaka
3014b2f322 This patch adds a flag in MCAsmInfo that indicates whether dwarf register 
numbers should be printed instead of symbolic register names in
MCAsmStreamer::EmitRegisterName. This is necessary because some versions of
GNU assembler won't accept code in which symbolic register names are used in
cfi directives. There is no change in behavior unless the flag is explicitly
set to true by a backend.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134635 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 20:30:33 +00:00
Akira Hatanaka
17a2f8e551 Define class MipsMCInstLower. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134633 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 20:24:54 +00:00
Akira Hatanaka
aa08ea0530 Change visibility of MipsAsmPrinter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 20:10:52 +00:00
Akira Hatanaka
2091a0d8d2 Define class MipsMCSymbolRefExpr. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134629 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 19:27:22 +00:00
Akira Hatanaka
4d1abf1a38 Simplify MipsRegisterInfo::eliminateFrameIndex. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134628 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 19:13:09 +00:00
Evan Cheng
4761a8d654 Rewrite comment in English. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134627 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 19:09:06 +00:00
Evan Cheng
963b03c1a9 Rename attribute 'thumb' to a more descriptive 'thumb-mode'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 19:05:12 +00:00
Akira Hatanaka
d3ac47f805 Reverse order of operands of address operand mem so that the base operand comes 
before the offset. This change will enable simplification of function
MipsRegisterInfo::eliminateFrameIndex.





git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134625 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 18:57:00 +00:00
Akira Hatanaka
e280519ba6 Add missing return statement. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134622 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 18:27:36 +00:00
Devang Patel
9194c6716b If known DebugLocs do not match then two DBG_VALUE machine instructions are not identical. For example, 
DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:32:10 ]
        DBG_VALUE 3.310000e+02, 0, !"ds"; dbg:sse.stepfft.c:138:18 @[ sse.stepfft.c:31:10 ]

These two MIs represent identical value, 3.31...,  for one variable, ds, but they are not identical because the represent two separate instances of inlined variable "ds". 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134620 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 17:45:33 +00:00
Joerg Sonnenberger
f86b76ead7 Recognize mipseb as alias for mips for symmetry with mipsel. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134617 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 16:53:52 +00:00