Commit Graph

10859 Commits

Author SHA1 Message Date
Chris Lattner
0b79cfee15 revert r114386 now that address modes work correctly, we get a nice
call through gs-relative memory now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114510 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 00:11:31 +00:00
Chris Lattner
93c4a5bef7 give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114508 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:59:42 +00:00
Chris Lattner
b72d53d8ef filecheckize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114507 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:57:27 +00:00
Evan Cheng
691e64a54c OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114506 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 23:49:07 +00:00
Owen Anderson
8614167572 Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes
irrelevant, but add a new test for the new, improved functionality.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 22:51:46 +00:00
Devang Patel
161f0caaf9 Use FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114475 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 20:50:32 +00:00
Owen Anderson
c004eec71b When adding the carry bit to another value on X86, exploit the fact that the carry-materialization
(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 18:41:19 +00:00
Mikhail Glushenkov
46aa524f0d llvmc: Allow multiple output languages.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 14:59:42 +00:00
Chris Lattner
08bad54baf fix rdar://8453210, a crash handling a call through a GS relative load.
For now, just disable folding the load into the call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114386 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 03:37:00 +00:00
Rafael Espindola
f7c10a3cff Implement support for .local and its "interesting" interactions with .comm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114382 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-21 00:24:38 +00:00
Evan Cheng
44be1a8d66 Enable machine sinking critical edge splitting. e.g.
define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 22:52:00 +00:00
Owen Anderson
765fd9c62d CombinerAA is now reordering these stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114354 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 20:56:29 +00:00
Owen Anderson
4a9f150926 When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore,
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.

This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114348 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 20:39:59 +00:00
Jim Grosbach
1dc335a79f Simplify ARM callee-saved register handling by removing the distinction
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 19:32:20 +00:00
Rafael Espindola
43779dcfef Produce a R_X86_64_32 when the value is >=0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114339 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-20 19:20:47 +00:00
NAKAMURA Takumi
e6af80d11d test/CodeGen/X86: Add explicit triplet -mtriple=i686-linux to 3 tests incompatible to Win32 codegen.
r114297 raises 3 failures. They might fail also on mingw.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114317 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-19 21:58:55 +00:00
Eric Christopher
50880d08ec Add the exit instruction to the PTX target.
Patch by Che-Liang Chiou <clchiou@gmail.com>!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114294 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 18:52:28 +00:00
Rafael Espindola
ad49cf5866 Make sure the STT_FILE symbol is the first one in the symbol table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114285 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 15:03:21 +00:00
Owen Anderson
14ac1dd2be Invert the logic of reachesChainWithoutSideEffects(). What we want to check is that there is
NO path to the destination containing side effects, not that SOME path contains no side effects.
In  practice, this only manifests with CombinerAA enabled, because otherwise the chain has little
to no branching, so "any" is effectively equivalent to "all".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114268 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 04:45:14 +00:00
Rafael Espindola
d3dce16ffe Add test that was missing in my previous commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114248 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:37:27 +00:00
Dan Gohman
23110b3c16 Attempt to XFAIL this test on arm-linux, which is inexplicably failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 00:04:37 +00:00
Benjamin Kramer
92aa1f7123 Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 23:48:07 +00:00
Bob Wilson
75f0288b7d Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert.  Radar 8407927.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff Teach the (non-MC) instruction printer to use the cannonical names for push/pop,
and shift instructions on ARM. Update the tests to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:36:38 +00:00
Evan Cheng
6edb0eac87 Teach machine sink to
1) Do forward copy propagation. This makes it easier to estimate the cost of the
   instruction being sunk.
2) Break critical edges on demand, including cases where the value is used by
   PHI nodes.
Critical edge splitting is not yet enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 22:28:18 +00:00
Jim Grosbach
9ce75625eb Update tests to handle MC-inst instruction printing of shift operations. The
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:58:46 +00:00
Jim Grosbach
db664ad71e FileCheck-ize
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114218 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 21:46:16 +00:00
Jim Grosbach
1aaf4cb393 Move thumb2 tests to the thumb2 directory
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:34:09 +00:00
Jim Grosbach
c0911c3b3e tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:27:26 +00:00
Dan Gohman
4e51a12ed7 Fix this test to avoid an "inexact" fold.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114202 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:25:43 +00:00
Dan Gohman
d8c0a51362 Avoid emitting a PIC base register if no PIC addresses are needed.
This fixes rdar://8396318.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:24:24 +00:00
Jim Grosbach
d4ef24344a tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114200 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:21:03 +00:00
Jim Grosbach
48afc24274 tweak test to check instructions rather than relying on the comment string
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114199 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:17:41 +00:00
Dan Gohman
80d6c96c2a Fix this test so that folding doesn't depend on a potentially
"inexact" result.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 20:15:53 +00:00
Chris Lattner
40cc3f8783 fix rdar://8444631 - encoder crash on 'enter'
What a weird instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:02:29 +00:00
Daniel Dunbar
23bea41ec6 MC/Mach-O/i386: Fix a crash in relocation handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114176 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 15:21:50 +00:00
Oscar Fuentes
c6a8c0580b tests/CMakeLists.txt: use configure_file' instead of sed'.
The Windows users will appreciate this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114158 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 03:22:21 +00:00
Daniel Dunbar
cceba83893 MC/AsmParser: Add support for 'a + 4@GOTPCREL' and friends, by reconsing the
expression to include the modifier.
 - Gross, but this a corner case we don't expect to see often in practice, but
   it is worth accepting.
 - Also improves diagnostics on invalid modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 02:47:07 +00:00
Dan Gohman
8ee731f2ce Fix the folding of floating-point math library calls, like sin(infinity),
so that it detects errors on platforms where libm doesn't set errno.
It's still subject to host libm details though.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114148 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 01:38:06 +00:00
Devang Patel
1905a18abc If FE forgot to provide a file name (usually it uses "stdin" as name in such situation) then make one up to ensure that debug info is not malformed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114119 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 20:57:49 +00:00
Chris Lattner
35aa94b229 fix rdar://8438816 - unrecognized 'fildq' instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114116 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 20:46:38 +00:00
Rafael Espindola
71859c640f Print the address of sections as 0 and create the metadata sections in the
same order as gnu as.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114109 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 19:46:31 +00:00
Owen Anderson
b86f57c606 Add missing RUN line to this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114106 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 18:46:23 +00:00
Dale Johannesen
677c6ecd08 When substituting sunkaddrs into indirect arguments an asm, we were
walking the asm arguments once and stashing their Values.  This is
wrong because the same memory location can be in the list twice, and
if the first one has a sunkaddr substituted, the stashed value for the
second one will be wrong (use-after-free).  PR 8154.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114104 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 18:30:55 +00:00
Owen Anderson
c2ce21ad51 It is possible, under specific circumstances involving ptrtoint ConstantExpr's, for LVI to end up trying to merge
a Constant into a ConstantRange.  Handle this conservatively for now, rather than asserting.  The testcase is
more complex that I would like, but the manifestation of the problem is sensitive to iteration orders and the state of the
LVI cache, and I have not been able to reproduce it with manually constructed or simplified cases.

Fixes PR8162.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114103 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 18:28:33 +00:00
Owen Anderson
4b91c3ac96 Fix PR8161, in which an unreachable loop causes recursive instruction simplification to try
to replace an instruction with itself.  Add a predicate to the simplifier to prevent this case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:42:36 +00:00
Rafael Espindola
34e3d0cfe5 Make sure that names like .note.GNU-stack are accepted as valid section names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 17:05:55 +00:00
Rafael Espindola
2ea2ac798b Add support for the .zero directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114077 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 15:03:59 +00:00
Kalle Raiskila
1cd1b0b283 Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
	or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.

Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-16 12:29:33 +00:00
Jim Grosbach
b9dadc9066 add a test of an edge case value for the FP immediate (needs all digits of
precision)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114028 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 21:52:13 +00:00