Commit Graph

65129 Commits

Author SHA1 Message Date
Reed Kotler
1101cde770 Disable some code that is causing some warnings. It's in the process
of being converted and this path is not relevant to anything at this time
so I have just disabled it for a few days while I'm at the LLVM conference
and don't have time to complete it or properly fix it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194201 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 11:56:33 +00:00
Vincent Lejeune
69239a98b6 R600: Fix LowerUDIVREM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194153 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 17:36:04 +00:00
Amara Emerson
1b484aba80 [AArch64] Remove NEON from "generic" CPU target.
We can change this back when NEON support is complete and ready to become
enabled by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 16:19:08 +00:00
Richard Sandiford
d975a82e08 [SystemZ] Handle vectors in getSetCCResultType
I don't have a standalone testcase for this, but it should allow r193676
to be reapplied.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 12:16:02 +00:00
Vladimir Medic
2263a2ca72 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:27:05 +00:00
Peter Zotov
54edcc2682 Add newline at EOF in DynamicLibrary.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:12:46 +00:00
Peter Zotov
1acb2127ba [llvm-c] Improve TargetMachine bindings
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 10:25:18 +00:00
Peter Zotov
92198d4f0a [llvm-c] Specify explicit namespace in LLVMLoadLibraryPermanently
Presence of using namespace llvm depended on several #ifdef's, and
this broke the build on mswin32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194142 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:45:58 +00:00
Peter Zotov
87265f9792 [llvm-c] Expose LLVMLoadLibraryPermanently
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194139 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:31 +00:00
Peter Zotov
c6099db476 [llvm-c] Expose IRReader interface
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:15 +00:00
Peter Zotov
14bbb1d9b0 [llvm-c] Implement LLVMPrintValueToString
Original patch by Chris Wailes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:01 +00:00
Reed Kotler
7851bc1871 Fix definition for Mips16 pc relative load word instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 04:29:52 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:25:49 +00:00
Andrew Trick
10bb82e54f Rewrite SCEV's backedge taken count computation.
Patch by Michele Scandale!

Rewrite of the functions used to compute the backedge taken count of a
loop on LT and GT comparisons.

I decided to split the handling of LT and GT cases becasue the trick
"a > b == -a < -b" in some cases prevents the trip count computation
due to the multiplication by -1 on the two operands of the
comparison. This issue comes from the conservative computation of
value range of SCEVs: taking the negative SCEV of an expression that
have a small positive range (e.g. [0,31]), we would have a SCEV with a
fullset as value range.

Indeed, in the new rewritten function I tried to better handle the
maximum backedge taken count computation when MAX/MIN expression are
used to handle the cases where no entry guard is found.

Some test have been modified in order to check the new value correctly
(I manually check them and reasoning on possible overflow the new
values seem correct).

I finally added a new test case related to the multiplication by -1
issue on GT comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:08:26 +00:00
Reed Kotler
c9080b7bc9 Get rid of current calculation function and adjustment scheme
from MipsConstantIslands. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194108 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 23:36:58 +00:00
Andrew Trick
dc8224def3 Slightly change the way stackmap and patchpoint intrinsics are lowered.
MorphNodeTo is not safe to call during DAG building. It eagerly
deletes dependent DAG nodes which invalidates the NodeMap. We could
expose a safe interface for morphing nodes, but I don't think it's
worth it. Just create a new MachineNode and replaceAllUsesWith.

My understaning of the SD design has been that we want to support
early target opcode selection. That isn't very well supported, but
generally works. It seems reasonable to rely on this feature even if
it isn't widely used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 22:44:04 +00:00
Reed Kotler
14cfb10174 Get rid of all references to soimm in MipsConstantIslands pass because
we don't have such an operand.
Suprisingly enough, this is never actually accounted for in the 
ARM version when determining offset ranges. In both places there is the
comment:
-    // FIXME: Make use full range of soimm values.
(soimm = shift operand immediate).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194101 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 22:34:29 +00:00
Reed Kotler
1fa282d635 Cleanup getUserOffset. Issues related to inline assembler length and
alignment will be handled differently than in ARM constant islands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194096 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:39:57 +00:00
Tim Northover
f635ab8eab ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:36:02 +00:00
Rafael Espindola
af9e8e60ae Use error_code in GVMaterializer.
They just propagate out the bitcode reader error, so we don't need a new enum.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 19:36:34 +00:00
Jiangning Liu
3ff3a8aa75 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 17:42:05 +00:00
Rafael Espindola
e05744ba85 Convert FindFunctionInStream to return an error_code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 17:16:08 +00:00
Michael Gottesman
f23af8bfd8 [objc-arc] Convert the one directional retain/release relation assert to a conditional check + fail.
Due to the previously added overflow checks, we can have a retain/release
relation that is one directional. This occurs specifically when we run into an
additive overflow causing us to drop state in only one direction. If that
occurs, we should bail and not optimize that retain/release instead of
asserting.

Apologies for the size of the testcase. It is necessary to cause the additive
cfg overflow to trigger.

rdar://15377890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 16:02:40 +00:00
Benjamin Kramer
a83342ba3b Silence GCC warning about dropping off a fully covered switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194077 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 13:45:09 +00:00
Reed Kotler
a2e6e6bcf8 Remove the word "thumb" from comments. Remove also an incorrect
command regarding the porting from the ARM version (was an old comment).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 12:04:37 +00:00
David Majnemer
8f198b0d60 X86 Disassembler: remove unused bool typedef-name
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194062 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 10:34:42 +00:00
Reed Kotler
c0e9800d45 Fix r194019 as requested by Eric Christopher.
Submit the basic port of the rest of ARM constant islands code to Mips. 
Two test cases are added which reflect the next level of functionality:
constants getting moved to water areas that are out of range from the
initial placement at the end of the function and basic blocks being split to
create water when none exists that can be used. There is a bunch of this
code that is not complete and has been marked with IN_PROGRESS. I will
finish cleaning this all up during the next week or two and submit the
rest of the test cases. I have elminated some code for dealing with
inline assembly because to me it unecessarily complicates things and
some of the newer features of llvm like function attributies and builtin
assembler give me better tools to solve the alignment issues created
there. Also, for Mips16 I even have the option of not doing constant
islands in the present of inline assembler if I chose. When everything
has been completed I will summarize the port and notify people that
are knowledgable regarding the ARM Constant Islands code so they can
review it in it's entirety if they wish.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 08:14:14 +00:00
Craig Topper
f6157f00db Lift alignment restrictions on load folding for a significant portion of AVX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194048 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 06:31:43 +00:00
Hao Liu
591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post).
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 03:39:32 +00:00
Kevin Qin
8263dcdf23 Implemented aarch64 neon intrinsic vcopy_lane with float type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 02:03:59 +00:00
Yuchen Wu
f44533c65e Revert "llvm-cov: Added command-line option to change dir."
This reverts commit d8acf0078c.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 01:56:29 +00:00
Yuchen Wu
d8acf0078c llvm-cov: Added command-line option to change dir.
This will allow for much easier testing when the input files are in a
different folder from the test script.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 01:20:41 +00:00
Yuchen Wu
e85959cb2c Support for reading run counts in llvm-cov.
This patch enables llvm-cov to correctly output the run count stored in
the GCDA file. GCOVProfiling currently does not generate this
information, so the GCDA run data had to be hacked on from a GCDA file
generated by gcc. This is corrected by a subsequent patch.

With the run and program data included, both llvm-cov and gcov produced
the same output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 01:11:58 +00:00
Hal Finkel
c88eb08d02 Add a runtime unrolling parameter to the LoopUnroll pass constructor
As with the other loop unrolling parameters (the unrolling threshold, partial
unrolling, etc.) runtime unrolling can now also be controlled via the
constructor. This will be necessary for moving non-trivial unrolling late in
the pass manager (after loop vectorization).

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194027 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 00:08:03 +00:00
NAKAMURA Takumi
225f35a87c Revert r194019 to r194021, "Submit the basic port of the rest of ARM constant islands code to Mips."
It broke -Asserts build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 23:14:36 +00:00
Tim Northover
e53abc2072 ARM: remove unnecessary state-tracking during frame lowering.
ResolveFrameIndex had what appeared to be a very nasty hack for when the
frame-index referred to a callee-saved register. In this case it "adjusted" the
offset so that the address was correct if (and only if) the MachineInstr
immediately followed the respective push.

This "worked" for all forms of GPR & DPR but was only ever used to set the
frame pointer itself, and once this was put in a more sensible location the
entire state-tracking machinery it relied on became redundant. So I stripped
it.

The only wrinkle is that "add r7, sp, #0" might theoretically be slower (need
an actual ALU slot) compared to "mov r7, sp" so I added a micro-optimisation
that also makes emitARMRegUpdate and emitT2RegUpdate also work when NumBytes ==
0.

No test changes since there shouldn't be any functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 23:04:15 +00:00
Tim Northover
627ef0cf5e AArch64: use default asm operand printing when modifier inapplicable
If an inline assembly operand has multiple constraints (e.g. "Ir" for immediate
or register) and an operand modifier (E.g. "w" for "print register as wN") then
we need to decide behaviour when the modifier doesn't apply to the constraint.

Previousely produced some combination of an assertion failure and a fatal
error. GCC's behaviour appears to be to ignore the modifier and print the
operand in the default way. This patch should implement that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194024 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 23:04:07 +00:00
Reed Kotler
ba29378fdc Make sure we don't get a warning from this variable that is only used
when compiling with DEBUG.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194021 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 22:42:17 +00:00
Reed Kotler
1ef9083122 Submit the basic port of the rest of ARM constant islands code to Mips.
Two test cases are added which reflect the next level of functionality:
constants getting moved to water areas that are out of range from the
initial placement at the end of the function and basic blocks being split to
create water when none exists that can be used. There is a bunch of this
code that is not complete and has been marked with IN_PROGRESS. I will
finish cleaning this all up during the next week or two and submit the
rest of the test cases. I have elminated some code for dealing with
inline assembly because to me it unecessarily complicates things and
some of the newer features of llvm like function attributies and builtin
assembler give me better tools to solve the alignment issues created
there. Also, for Mips16 I even have the option of not doing constant
islands in the present of inline assembler if I chose.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194019 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 22:11:25 +00:00
Shuxin Yang
6f744ee498 Remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194017 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 21:44:01 +00:00
Eric Christopher
3faf43fc66 Check for both styles of clobbers, those produced by dragonegg and
those produced by clang for the inline asm bswap conversion.

Modified from a patch by Chris Smowton.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194016 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 21:41:21 +00:00
Benjamin Kramer
63d8f88686 SLPVectorizer: Use properlyDominates to satisfy the irreflexivity of a strict weak ordering.
STL debug mode checks this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194015 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 21:34:55 +00:00
Matt Arsenault
896a885f21 Fix another constant folding address space place I missed.
This fixes an assertion failure with a different sized address space.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 20:46:52 +00:00
Matt Arsenault
eba6d38448 Scalarize select vector arguments when extracted.
When the elements are extracted from a select on vectors
or a vector select, do the select on the extracted scalars
from the input if there is only one use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194013 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 20:36:06 +00:00
Jakub Staszak
42f2a6b41e Use startswith_lower() where possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 19:22:50 +00:00
Cameron McInally
2e58f1d4cf Add support for AVX512 masked vector blend intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 19:14:56 +00:00
Rafael Espindola
e076b5338a Change BitcodeReader to use error_code instead of bool + string.
In order to create an ObjectFile implementation that uses bitcode files, we
need to propagate the bitcode errors to the ObjectFile interface, so we need
to convert it to use the same error handling as ObjectFile: error_code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 16:16:24 +00:00
Zoran Jovanovic
5c042162be Support for microMIPS branch instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 14:53:22 +00:00
Benjamin Kramer
00e3be6134 X86: Add a description for AMD bdver3 aka Steamroller.
This is just bdver2 + FSGSBase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-04 10:29:20 +00:00