When a target instruction wants to set target-specific flags, it should simply
set bits in the TSFlags bit vector defined in the Instruction TableGen class.
This works well because TableGen resolves member references late:
class I : Instruction {
AddrMode AM = AddrModeNone;
let TSFlags{3-0} = AM.Value;
}
let AM = AddrMode4 in
def ADD : I;
TSFlags gets the expected bits from AddrMode4 in this example.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100384 91177308-0d34-0410-b5e6-96231b3b80d8
CodeGenDAGPatterns, where it can be used in other tablegen backends.
This allows the inference to be done for DAGISelEmitter so that it
gets accurate mayLoad/mayStore/isSimpleLoad flags.
This brings MemOperand functionality back to where it was before
48329. However, it doesn't solve the problem of anonymous patterns
which expand to code that does loads or stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
occured in a pattern, but failed miserably. The new code works for
any instruction that has a store in its pattern, including all the
x86 mem op mem instructions.
The only target-independent code that uses this is branch folding,
so this won't change anything in practice.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45648 91177308-0d34-0410-b5e6-96231b3b80d8
in one way: the generated tables require dynamic initialization for the
register classes. This will be fixed in a future patch.
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LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data. This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.
This should speed up the register allocator as well by reducing the dcache
footprint for this static data.
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