Commit Graph

20716 Commits

Author SHA1 Message Date
Hal Finkel
11af4b49b2 Add a dereferenceable attribute
This attribute indicates that the parameter or return pointer is
dereferenceable. Practically speaking, loads from such a pointer within the
associated byte range are safe to speculatively execute. Such pointer
parameters are common in source languages (C++ references, for example).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213385 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 15:51:28 +00:00
Daniel Sanders
a11bf68f6c Add MIPS Technologies to the vendors in llvm::Triple.
This is a prerequisite for checking for 'mti' and 'img' in a consistent way in
clang. Previously 'img' could use Triple::getVendor() but 'mti' could only use
Triple::getVendorName().



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 14:28:19 +00:00
Tim Northover
0afed03229 CodeGen: soften f16 type by default instead of marking legal.
Actual support for softening f16 operations is still limited, and can be added
when it's needed.  But Soften is much closer to being a useful thing to try
than keeping it Legal when no registers can actually hold such values.

Longer term, we probably want something between Soften and Promote semantics
for most targets, it'll be more efficient to promote the 4 basic operations to
f32 than libcall them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213372 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 12:41:46 +00:00
Renato Golin
03ac7db89d Refactor ARM subarchitecture parsing
Re-commit of a patch to rework the triple parsing on ARM to a more sane
model.

Patch by Gabor Ballabas.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 12:00:48 +00:00
Artyom Skrobov
11c20581d6 extracting swapStruct into include/llvm/Support/MachO.h (no functional change)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213361 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 09:26:16 +00:00
Hal Finkel
d0261683e8 Rename AlignAttribute to IntAttribute
Currently the only kind of integer IR attributes that we have are alignment
attributes, and so the attribute kind that takes an integer parameter is called
AlignAttr, but that will change (we'll soon be adding a dereferenceable
attribute that also takes an integer value). Accordingly, rename AlignAttribute
to IntAttribute (class names, enums, etc.).

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213352 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-18 06:51:55 +00:00
Kevin Enderby
c61aa0219e Add printing of Mach-O stabs in llvm-nm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213327 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 22:47:16 +00:00
Nico Weber
c1ef24ce39 ms inline asm: Don't add x86 segment registers to the clobber list.
Clang tries to check the clobber list but doesn't list segment registers in its
x86 register list. This fixes PR20343.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213303 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 20:24:55 +00:00
Alp Toker
3cf9f37312 Drop the udis86 wrapper from llvm::sys
This optional dependency on the udis86 library was added some time back to aid
JIT development, but doesn't make much sense to link into LLVM binaries these
days.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213300 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 20:05:29 +00:00
Matt Arsenault
15865afcf7 Fix typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213285 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 17:50:22 +00:00
Justin Holewinski
d6663f565c [NVPTX] Add more surface/texture intrinsics, including CUDA unified texture fetch
This also uses TSFlags to mark machine instructions that are surface/texture
accesses, as well as the vector width for surface operations.  This is used
to simplify some of the switch statements that need to detect surface/texture
instructions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213256 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:59:04 +00:00
Tim Northover
6c701b9aca CodeGen: generate single libcall for fptrunc -> f16 operations.
Previously we asserted on this code. Currently compiler-rt doesn't
actually implement any of these new libcalls, but external help is
pretty much the only viable option for LLVM.

I've followed the much more generic "__truncST2" naming, as opposed to
the odd name for f32 -> f16 truncation. This can obviously be changed
later, or overridden by any targets that need to.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213252 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 11:12:12 +00:00
Tim Northover
3e61ccdded CodeGen: extend f16 conversions to permit types > float.
This makes the two intrinsics @llvm.convert.from.f16 and
@llvm.convert.to.f16 accept types other than simple "float". This is
only strictly needed for the truncate operation, since otherwise
double rounding occurs and there's no way to represent the strict IEEE
conversion. However, for symmetry we allow larger types in the extend
too.

During legalization, we can expand an "fp16_to_double" operation into
two extends for convenience, but abort when the truncate isn't legal. A new
libcall is probably needed here.

Even after this commit, various target tweaks are needed to actually use the
extended intrinsics. I've put these into separate commits for clarity, so there
are no actual tests of f64 conversion here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213248 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:51:23 +00:00
Yi Kong
f33a30cdd0 Port memory barriers intrinsics to AArch64
Memory barrier __builtin_arm_[dmb, dsb, isb] intrinsics are required to
implement their corresponding ACLE and MSVC intrinsics.

This patch ports ARM dmb, dsb, isb intrinsic to AArch64.

Differential Revision: http://reviews.llvm.org/D4520


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213247 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 10:50:20 +00:00
Saleem Abdulrasool
adcb2d1636 MC: make WinEH opcode an opaque value
This makes the opcode an opaque value (unsigned int) rather than the
enumeration.  This permits the use of target specific operands.

Split out the generic type into a MCWinEH header and add a supporting
MCWin64EH::Instruction to abstract out the selection of the opcode and
construction of the actual instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213221 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 03:08:50 +00:00
Hal Finkel
8f609696e0 Improve BasicAA CS-CS queries (redux)
This reverts, "r213024 - Revert r212572 "improve BasicAA CS-CS queries", it
causes PR20303." with a fix for the bug in pr20303. As it turned out, the
relevant code was both wrong and over-conservative (because, as with the code
it replaced, it would return the overall ModRef mask even if just Ref had been
implied by the argument aliasing results). Hopefully, this correctly fixes both
problems.

Thanks to Nick Lewycky for reducing the test case for pr20303 (which I've
cleaned up a little and added in DSE's test directory). The BasicAA test has
also been updated to check for this error.

Original commit message:

BasicAA contains knowledge of certain intrinsics, such as memcpy and memset,
and uses that information to form more-accurate answers to CallSite vs. Loc
ModRef queries. Unfortunately, it did not use this information when answering
CallSite vs. CallSite queries.

Generically, when an intrinsic takes one or more pointers and the intrinsic is
marked only to read/write from its arguments, the offset/size is unknown. As a
result, the generic code that answers CallSite vs. CallSite (and CallSite vs.
Loc) queries in AA uses UnknownSize when forming Locs from an intrinsic's
arguments. While BasicAA's CallSite vs. Loc override could use more-accurate
size information for some intrinsics, it did not do the same for CallSite vs.
CallSite queries.

This change refactors the intrinsic-specific logic in BasicAA into a generic AA
query function: getArgLocation, which is overridden by BasicAA to supply the
intrinsic-specific knowledge, and used by AA's generic implementation. This
allows the intrinsic-specific knowledge to be used by both CallSite vs. Loc and
CallSite vs. CallSite queries, and simplifies the BasicAA implementation.

Currently, only one function, Mac's memset_pattern16, is handled by BasicAA
(all the rest are intrinsics). As a side-effect of this refactoring, BasicAA's
getModRefBehavior override now also returns OnlyAccessesArgumentPointees for
this function (which is an improvement).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213219 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 01:28:25 +00:00
Chris Bieneman
ec7a144603 [RegisterCoalescer] Moving the RegisterCoalescer subtarget hook onto the TargetRegisterInfo instead of the TargetSubtargetInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213188 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-16 20:13:31 +00:00
Reid Kleckner
55a421f98d Roundtrip the inalloca bit on allocas through bitcode
This was an oversight in the original support.  As it is, I stuffed this
bit into the alignment.  The alignment is stored in log2 form, so it
doesn't need more than 5 bits, given that Value::MaximumAlignment is 1
<< 29.

Reviewers: nicholas

Differential Revision: http://reviews.llvm.org/D3943

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213118 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-16 01:34:27 +00:00
Tyler Nowicki
77f03040d5 Emit warnings if vectorization is forced and fails.
This patch modifies the existing DiagnosticInfo system to create a generic base
class that is inherited to produce diagnostic-based warnings. This is used by
the loop vectorizer to trigger a warning when vectorization is forced and
fails. Several tests have been added to verify this behavior.

Reviewed by: Arnold Schwaighofer


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213110 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-16 00:36:00 +00:00
Juergen Ributzka
7e752a311a Remove TLI from isInTailCallPosition's arguments. NFC.
There is no need to pass on TLI separately to the function. As Eric pointed out
the Target Machine already provides everything we need.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213108 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-16 00:01:22 +00:00
Sanjay Patel
f7e042324a Move Post RA Scheduling flag bit into SchedMachineModel
Refactoring; no functional changes intended

    Removed PostRAScheduler bits from subtargets (X86, ARM).
    Added PostRAScheduler bit to MCSchedModel class.
    This bit is set by a CPU's scheduling model (if it exists).
    Removed enablePostRAScheduler() function from TargetSubtargetInfo and subclasses.
    Fixed the existing enablePostMachineScheduler() method to use the MCSchedModel (was just returning false!).
    Added methods to TargetSubtargetInfo to allow overrides for AntiDepBreakMode, CriticalPathRCs, and OptLevel for PostRAScheduling.
    Added enablePostRAScheduler() function to PostRAScheduler class which queries the subtarget for the above values.
    Preserved existing scheduler behavior for ARM, MIPS, PPC, and X86: 
       a. ARM overrides the CPU's postRA settings by enabling postRA for any non-Thumb or Thumb2 subtarget. 
       b. MIPS overrides the CPU's postRA settings by enabling postRA for everything. 
       c. PPC overrides the CPU's postRA settings by enabling postRA for everything. 
       d. X86 is the only target that actually has postRA specified via sched model info.

Differential Revision: http://reviews.llvm.org/D4217


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213101 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 22:39:58 +00:00
Duncan P. N. Exon Smith
c12ce2b661 ADT: Add MapVector::remove_if
Add a `MapVector::remove_if()` that erases items in bulk in linear time,
as opposed to quadratic time for repeated calls to `MapVector::erase()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 20:24:56 +00:00
Lang Hames
58d03b3e08 [RuntimeDyld] Revert r211652 - MachO object GDB registration support.
The registration scheme used in r211652 violated the read-only contract of
MemoryBuffer. This caused crashes in llvm-rtdyld where macho objects were backed
by read-only mmap'd memory.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213086 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 19:35:22 +00:00
Duncan P. N. Exon Smith
d9ebc5991b ADT: Fix MapVector::erase()
Actually update the changed indexes in the map portion of `MapVector`
when erasing from the middle.  Add a unit test that checks for this.

Note that `MapVector::erase()` is a linear time operation (it was and
still is).  I'll commit a new method in a moment called
`MapVector::remove_if()` that deletes multiple entries in linear time,
which should be slightly less painful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213084 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 18:32:30 +00:00
Duncan P. N. Exon Smith
9f865ed141 ADT: Add "end namespace" comment
This keeps clang-format from deleting the preceding newline.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213082 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 18:06:56 +00:00
Chris Bieneman
01d8611240 [RegisterCoalescer] Add new subtarget hook allowing targets to opt-out of coalescing.
The coalescer is very aggressive at propagating constraints on the register classes, and the register allocator doesn’t know how to split sub-registers later to recover. This patch provides an escape valve for targets that encounter this problem to limit coalescing.

This patch also implements such for ARM to lower register pressure when using lots of large register classes. This works around PR18825.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213078 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 17:18:41 +00:00
Peter Collingbourne
ca3c5b8722 Give SplitBlockAndInsertIfThen the ability to update a domtree.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213045 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 04:40:27 +00:00
Nick Lewycky
5508cfd02c Revert r212572 "improve BasicAA CS-CS queries", it causes PR20303.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213024 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-15 00:53:38 +00:00
David Majnemer
38d8be1ad8 CodeGen: Stick constant pool entries in COMDAT sections for WinCOFF
COFF lacks a feature that other object file formats support: mergeable
sections.

To work around this, MSVC sticks constant pool entries in special COMDAT
sections so that each constant is in it's own section.  This permits
unused constants to be dropped and it also allows duplicate constants in
different translation units to get merged together.

This fixes PR20262.

Differential Revision: http://reviews.llvm.org/D4482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213006 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 22:57:27 +00:00
David Majnemer
a539d7b4df CodeGen: Add a getSectionKind method to MachineConstantPoolEntry
This is just a helper routine, no functionality has changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212993 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 22:06:29 +00:00
David Majnemer
74cb271d2b ADT: Surface LowerCase argument for utohexstr
The underlying function. utohex_buffer, already supports an argument for
deciding if the hex characters should be upper or lower case.  Expose an
identical argument for utohexstr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212991 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 21:56:54 +00:00
Sanjay Patel
c41eb0df9a removed circular definitions in comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212990 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 21:51:59 +00:00
Justin Bogner
f66fc53bc7 Support: Fix option handling when using cl::Required with aliasopt
Until now, attempting to create an alias of a required option would
complain if the user supplied the alias, because the required option
didn't have a value. Similarly, if you said the alias was required,
then using the base option would complain that the alias wasn't
supplied. Lastly, if you put required on both, *neither* option would
work.

By changning alias to overload addOccurrence and setting cl::Required
on the original option, we can get this to behave in a more useful
way. I've also added a test and updated a user that was getting this
wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212986 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 20:53:57 +00:00
Matt Arsenault
9f40cd7962 Add CreatePointerBitCastOrAddrSpaceCast to IRBuilder and co.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212962 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 17:24:35 +00:00
Matt Arsenault
e51c7372b3 Update comments to include addrspacecast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212961 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 17:24:31 +00:00
Matt Arsenault
8e44dbb0ef Remove GCC 3.3 workaround
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212960 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-14 17:11:20 +00:00
Saleem Abdulrasool
083db8b72c MC: make MCWin64EHInstruction a POD-like struct
This is the first of a number of changes designed to generalise
MCWin64EHInstruction to support different target architectures.  An ordered set
(vector) of these instructions is saved per frame to permit the emission of
information for Windows NT style unwinding.  The only bit of information which
is actually target specific here is the Opcode for the unwinding bytecode.  The
remainder of the information is simply generic information that is relevant to
the Windows NT unwinding model.

Remove the accessors for the fields, making them const and public instead.  Sink
the knowledge of the alias'ed name into the single source and sink a single-use
check method into the use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212914 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 19:03:45 +00:00
Saleem Abdulrasool
1f1e6e7884 MC: make DWARF and Windows unwinding handling more similar
Rename member variables and functions for the MCStreamer for DWARF-like
unwinding management.  Rename the Windows ones as well and make the naming and
handling similar across the two.  No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212912 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-13 19:03:36 +00:00
Matt Arsenault
8ef1fa761f Try to fix MSVC warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212889 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 23:16:26 +00:00
Matt Arsenault
bf9b767eb8 Try to fix MSVC build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212888 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 23:09:02 +00:00
Matt Arsenault
4118913074 Try to fix MSVC build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212886 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 22:19:49 +00:00
Matt Arsenault
661ca49da7 Templatify DominanceFrontier.
Theoretically this should now work for MachineBasicBlocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212885 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 21:59:52 +00:00
Saleem Abdulrasool
01c06d7954 AArch64: add support for llvm.aarch64.hint intrinsic
This adds a llvm.aarch64.hint intrinsic to mirror the llvm.arm.hint in order to
support the various hint intrinsic functions in the ACLE.

Add an optional pattern field that permits the subclass to specify the pattern
that matches the selection.  The intrinsic pattern is set as mayLoad, mayStore,
so overload the value for the definition of the hint instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212883 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 21:20:49 +00:00
Saleem Abdulrasool
8e69909cc2 MC: rename MCW64UnwindInfo to MCWinFrameInfo
This structure contains information related to the call frame used to generate
unwinding information.  Rename this to reflect the future use to represent the
shared state between various architectures for WinCFI information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212881 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 20:49:09 +00:00
Duncan P. N. Exon Smith
8ff8772676 BFI: Add constructor for Weight
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 00:26:00 +00:00
Duncan P. N. Exon Smith
d164a164ec BFI: Clean up BlockMass
Implementation is small now -- the interesting logic was moved to
`BranchProbability` a while ago.  Move it into `bfi_detail` and get rid
of the related TODOs.

I was originally planning to define it within `BlockFrequencyInfoImpl`
(or `BFIIBase`), but it seems cleaner in a namespace.  Besides,
`isPodLike` needs to be specialized before `BlockMass` can be used in
some of the other data structures, and there isn't a clear way to do
that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212866 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 00:21:30 +00:00
Reid Kleckner
e2729b9a98 Option: Propagate flags from groups to options in each group
This should make it easy to set a flag for a whole group of clang driver
options.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212865 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-12 00:18:58 +00:00
Duncan P. N. Exon Smith
1c224d8d88 BFI: Mark the end of namespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 23:56:50 +00:00
Juergen Ributzka
30f9ff4bee [FastISel] Add target-independent patchpoint intrinsic support. WIP.
This implements the target-independent lowering for the patchpoint
intrinsic. Targets have to implement the FastLowerCall
hook to support this intrinsic.

Related to <rdar://problem/17427052>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212849 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 22:19:02 +00:00
Juergen Ributzka
324b3fc7c8 [FastISel] Add basic infrastructure to support a target-independent call lowering hook in FastISel. WIP
The infrastructure mimics the call lowering we have already in place for
SelectionDAG, but with limitations. For example structure return demotion and
non-simple types are not supported (yet).

Currently every backend has its own implementation and duplicated code for call
lowering. There is also no specified interface that could be called from
target-independent code. The target-hook is opt-in and doesn't affect current
implementations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212848 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-11 22:01:42 +00:00