Commit Graph

6797 Commits

Author SHA1 Message Date
Rafael Espindola
15f1b66d64 Fix PR 4004 by including the call to __tls_get_addr in X86tlsaddr. This is not
very elegant, but neither is the tls specification :-(



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69968 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 12:59:40 +00:00
Rafael Espindola
15684b2955 Revert 69952. Causes testsuite failures on linux x86-64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69967 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 12:40:33 +00:00
Nate Begeman
b706d29f9c PR2957
ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask.  A value of -1 represents UNDEF.

In addition to eliminating the creation of illegal BUILD_VECTORS just to 
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.

A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69952 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-24 03:42:54 +00:00
David Greene
e8cf21e8e3 Make BinOps typed and require a type specifier for !nameconcat. This
allows binops to be used in typed contexts such as when passing
arguments to classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69921 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 21:25:15 +00:00
Dan Gohman
e41bc94bb1 Explicitly pass -tailcallopt=false to these tests so that they
work as intended no matter what the default setting of that
option is.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 19:39:41 +00:00
Dale Johannesen
4aa397c5bf Testcase for 69795.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69901 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 18:04:04 +00:00
Dan Gohman
e22d503ee5 Fix an error in this test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69893 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 15:22:28 +00:00
Dan Gohman
752ec7da50 Change SCEVExpander's expandCodeFor to provide more flexibility
with the persistent insertion point, and change IndVars to make
use of it. This fixes a bug where IndVars was holding on to a
stale insertion point and forcing the SCEVExpander to continue to
use it.

This fixes PR4038.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69892 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 15:16:49 +00:00
Nick Lewycky
5cd28fad15 Simplify trunc(extend(x)) in SCEVs, just for completeness. Also fix some odd
whitespace in the same file.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69870 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 05:15:08 +00:00
Owen Anderson
03dac74d40 Testcase for PR3909.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69868 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 04:33:42 +00:00
Owen Anderson
887fde88ca Testcase for PR2639.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69867 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 04:30:52 +00:00
Owen Anderson
d92395fe92 Testcase for PR2537.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69866 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 04:26:42 +00:00
Owen Anderson
f2a5c0a04c Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69865 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 04:24:19 +00:00
Owen Anderson
176aeb1afa Testcase for PR3085.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69863 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 04:21:14 +00:00
Owen Anderson
d49468aa50 Add testcase from PR3086.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69862 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 04:14:03 +00:00
Dan Gohman
ab192b71a6 Add more ulimit limits, to catch more kinds of runaway behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69847 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-23 00:28:31 +00:00
Evan Cheng
9c15949967 Make sure both operands have binary instructions have the same type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69844 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 23:39:28 +00:00
Evan Cheng
1abe64663e Avoid deferencing use_begin() if value does not have a use.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69836 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 22:45:37 +00:00
David Greene
5654613a01 Allow defm to inherit from multiple multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69832 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 22:17:51 +00:00
David Greene
c7cafcd815 Implement !nameconcat to concatenate strings and look up the resulting
name in the symbol table, returning an object.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69822 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 20:18:10 +00:00
Duncan Sands
d7b2f7ffce Testcase for PR2958.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69818 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 18:55:17 +00:00
David Greene
de444af6bb Implement multiclass inheritance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69810 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 16:42:54 +00:00
Dan Gohman
aabb04f527 SCEVExpander's InsertCastOfTo knows how to move existing cast
instructions in order to avoid inserting new ones. However, if
the cast instruction is the SCEVExpander's InsertPt, this
causes subsequently emitted instructions to be inserted near
the cast, and not at the location of the original insert point.
Fix this by adjusting the insert point in such cases.
This fixes PR4009.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69808 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 16:11:16 +00:00
Duncan Sands
4a0adb7686 These tests are x86 specific.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69798 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-22 10:39:51 +00:00
Evan Cheng
5b69ebac85 It has finally happened. Spiller is now using live interval info.
This fixes a very subtle bug. vr defined by an implicit_def is allowed overlap with any register since it doesn't actually modify anything. However, if it's used as a two-address use, its live range can be extended and it can be spilled. The spiller must take care not to emit a reload for the vn number that's defined by the implicit_def. This is both a correctness and performance issue.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69743 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21 22:46:52 +00:00
Dan Gohman
578ccf81e5 When turning (ashr(shl(x, n), n)) into sext(trunc(x)), the width of the
type to truncate to should be the number of bits of the value that are
preserved, not the number that are clobbered with sign-extension.
This fixes regressions in ldecod.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69704 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21 20:18:36 +00:00
Devang Patel
1d85a1f00b Test case for revision 69683.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69684 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21 17:21:01 +00:00
Chris Lattner
33e24adc3b fix a crash on a pointless but valid zero-length memset, rdar://6808691
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69680 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-21 16:52:12 +00:00
Evan Cheng
206d1856ad Added a linearscan register allocation optimization. When the register allocator spill an interval with multiple uses in the same basic block, it creates a different virtual register for each of the reloads. e.g.
%reg1498<def> = MOV32rm %reg1024, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg1024, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg1024, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

=>

        %reg1498<def> = MOV32rm %reg2036, 1, %reg0, 12, %reg0, Mem:LD(4,4) [sunkaddr39 + 0]
        %reg1506<def> = MOV32rm %reg2037, 1, %reg0, 8, %reg0, Mem:LD(4,4) [sunkaddr42 + 0]
        %reg1486<def> = MOV32rr %reg1506
        %reg1486<def> = XOR32rr %reg1486, %reg1498, %EFLAGS<imp-def,dead>
        %reg1510<def> = MOV32rm %reg2038, 1, %reg0, 4, %reg0, Mem:LD(4,4) [sunkaddr45 + 0]

From linearscan's point of view, each of reg2036, 2037, and 2038 are separate registers, each is "killed" after a single use. The reloaded register is available and it's often clobbered right away. e.g. In thise case reg1498 is allocated EAX while reg2036 is allocated RAX. This means we end up with multiple reloads from the same stack slot in the same basic block.

Now linearscan recognize there are other reloads from same SS in the same BB. So it'll "downgrade" RAX (and its aliases) after reg2036 is allocated until the next reload (reg2037) is done. This greatly increase the likihood reloads from SS are reused.

This speeds up sha1 from OpenSSL by 5.8%. It is also an across the board win for SPEC2000 and 2006.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69585 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-20 08:01:12 +00:00
Chris Lattner
9dcab2fe8e testcase for PR3898
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69473 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 20:49:22 +00:00
Duncan Sands
b10b5ac8d9 Don't try to make BUILD_VECTOR operands have the same
type as the vector element type: allow them to be of
a wider integer type than the element type all the way
through the system, and not just as far as LegalizeDAG.
This should be safe because it used to be this way
(the old type legalizer would produce such nodes), so
backends should be able to handle it.  In fact only
targets which have legal vector types with an illegal
promoted element type will ever see this (eg: <4 x i16>
on ppc).  This fixes a regression with the new type
legalizer (vec_splat.ll).  Also, treat SCALAR_TO_VECTOR
the same as BUILD_VECTOR.  After all, it is just a
special case of BUILD_VECTOR.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69467 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 20:16:54 +00:00
Dale Johannesen
2cf68d4d23 Adjust XFAIL syntax, maybe that will help. The other
way worked for me...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69414 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 02:01:23 +00:00
Dale Johannesen
f4948450d1 patch 69408 breaks this by removing the opportunity
for the optimization it's testing to kick in (although
it improves the code, getting rid of all spills).
I don't understand the optimization well enough to
rescue the test, so XFAILing.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69409 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-18 00:11:50 +00:00
Bob Wilson
7eb793dd09 Rename file to have the correct suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69380 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 20:40:20 +00:00
Bob Wilson
1f595bb429 Use CallConvLower.h and TableGen descriptions of the calling conventions
for ARM.  Patch by Sandeep Patel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69371 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 19:07:39 +00:00
Rafael Espindola
2ee3db3003 For general dynamic TLS access we must use
leaq	foo@TLSGD(%rip), %rdi

as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69350 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 14:35:58 +00:00
Evan Cheng
276b77e66c Teach spiller to unfold instructions which modref spill slot when a scratch
register is available and when it's profitable.

e.g.
     xorq  %r12<kill>, %r13
     addq  %rax, -184(%rbp)
     addq  %r13, -184(%rbp)
==>
     xorq  %r12<kill>, %r13
     movq  -184(%rbp), %r12
     addq  %rax, %r12
     addq  %r13, %r12
     movq  %r12, -184(%rbp)

Two more instructions, but fewer memory accesses. It can also open up
opportunities for more optimizations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69341 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-17 01:29:40 +00:00
Rafael Espindola
7c36683fa3 fix PR3995. A scale must be 1, 2, 4 or 8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69284 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16 12:34:53 +00:00
Dan Gohman
2d1be87ee4 Expand GEPs in ScalarEvolution expressions. SCEV expressions can now
have pointer types, though in contrast to C pointer types, SCEV
addition is never implicitly scaled. This not only eliminates the
need for special code like IndVars' EliminatePointerRecurrence
and LSR's own GEP expansion code, it also does a better job because
it lets the normal optimizations handle pointer expressions just
like integer expressions.

Also, since LLVM IR GEPs can't directly index into multi-dimensional
VLAs, moving the GEP analysis out of client code and into the SCEV
framework makes it easier for clients to handle multi-dimensional
VLAs the same way as other arrays.

Some existing regression tests show improved optimization.
test/CodeGen/ARM/2007-03-13-InstrSched.ll in particular improved to
the point where if-conversion started kicking in; I turned it off
for this test to preserve the intent of the test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69258 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16 03:18:22 +00:00
Dale Johannesen
764eccf025 Another testcase for IV shortening.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69247 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-16 00:45:21 +00:00
Bill Wendling
dd9f523997 Check for alignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69140 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 04:51:05 +00:00
Dale Johannesen
dd1f9e4bf6 Enhance induction variable code to remove the
sext around sext(shorter IV + constant), using a
longer IV instead, when it can figure out the
add can't overflow.  This comes up a lot in
subscripting; mainly affects 64 bit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69123 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 01:10:12 +00:00
Devang Patel
517576d6f9 While inlining, clone llvm.dbg.func.start intrinsic and adjust
llvm.dbg.region.end instrinsic. This nested llvm.dbg.func.start/llvm.dbg.region.end pair now enables DW_TAG_inlined_subroutine support in code generator.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69118 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 00:17:06 +00:00
Bill Wendling
1759f5e3bf Testcase for r69104.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69110 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 00:04:11 +00:00
Evan Cheng
df2f1189a3 Optimize conditional branch on i1 phis with non-constant inputs.
This turns:

eq:
        %3 = icmp eq i32 %1, %2
        br label %join

ne:
        %4 = icmp ne i32 %1, %2
        br label %join

join:
        %5 = phi i1 [%3, %eq], [%4, %ne]
        br i1 %5, label %yes, label %no

=>

eq:
        %3 = icmp eq i32 %1, %2
        br i1 %3, label %yes, label %no

ne:
        %4 = icmp ne i32 %1, %2
        br i1 %4, label %yes, label %no


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69102 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 23:40:03 +00:00
Dan Gohman
5b9c31841f Fix the RUN lines so that this test actually tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69096 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 22:50:17 +00:00
Dan Gohman
62ad138d70 For the h-register addressing-mode trick, use the correct value for
any non-address uses of the address value. This fixes 186.crafty.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69094 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 22:45:05 +00:00
Dan Gohman
5ec3b427c8 When the result of an EXTRACT_SUBREG, INSERT_SUBREG, or SUBREG_TO_REG
operator is used by a CopyToReg to export the value to a different
block, don't reuse the CopyToReg's register for the subreg operation
result if the register isn't precisely the right class for the
subreg operation.

Also, rename the h-registers.ll test, now that there are more
than one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69087 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 22:17:14 +00:00
Evan Cheng
b3f5bfe37f Some of GR8_NOREX registers are only available in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 16:57:43 +00:00
Dale Johannesen
442b7bfc80 Use the output of the asm so the optimizer won't
delete it.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69018 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-14 01:51:40 +00:00