Bob Wilson
f6a4d3c2f3
Avoid write-after-write issue hazards for Cortex-A9.
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Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.
This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-19 18:11:45 +00:00
Evan Cheng
7e2fe9150f
Re-commit 117518 and 117519 now that ARM MC test failures are out of the way.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 06:47:08 +00:00
Evan Cheng
9e08ee5d16
Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 02:00:25 +00:00
Evan Cheng
0104d9de04
- Assign load / store with shifter op address modes the right itinerary classes.
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- For now, loads of [r, r] addressing mode is the same as the
[r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
is "free".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-28 01:49:06 +00:00
Evan Cheng
f7d87ee158
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 00:43:17 +00:00
Jim Grosbach
7ec7a0e96b
switch the flag for using NEON for SP floating point to a subtarget 'feature'.
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Re-commit. This time complete with testsuite updates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 23:47:34 +00:00
Edward O'Callaghan
11cc4fab52
Convert ARM tests to FileCheck for PR5307.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89593 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-22 14:23:33 +00:00
Jim Grosbach
e5165490b7
Use Unified Assembly Syntax for the ARM backend.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 00:11:35 +00:00
David Goodwin
9843a93e83
Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-01 22:19:57 +00:00
Dan Gohman
fce288fc91
Eliminate more uses of llvm-as and llvm-dis.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81293 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-09 00:09:15 +00:00
David Goodwin
767a952a6f
Make NEON single-precision FP support the default for cortex-a8 (again).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78430 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-07 23:32:33 +00:00
David Goodwin
42a83f2d15
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-04 17:53:06 +00:00
