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17 Commits

Author SHA1 Message Date
Craig Topper
3457506fb9 Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201507 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-17 10:03:43 +00:00
Craig Topper
45e6393241 Add more X86 FP stack disassembler test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198268 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 22:51:53 +00:00
Craig Topper
5cbbd7e1a5 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-31 17:21:44 +00:00
Craig Topper
8e121843c1 Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 01:42:32 +00:00
Craig Topper
b9bc43852c Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 05:53:50 +00:00
Craig Topper
e778f82a1e Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 07:19:47 +00:00
Craig Topper
36a9b31b98 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 04:28:06 +00:00
Ben Langmuir
a247e9d42b Add the remaining Intel SHA instructions 
Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-14 15:03:21 +00:00
Ben Langmuir
1f1bd9a54d Partial support for Intel SHA Extensions (sha1rnds4) 
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-12 15:51:31 +00:00
Kevin Enderby
877d123bdb Fix the move to/from accumulator register instructions that use a full 64-bit 
absolute address encoded in the instruction.

rdar://8612627 and rdar://14299221


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186878 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-07-22 21:25:31 +00:00
Michael Liao
02d2e61252 Add CLAC/STAC instruction encoding/decoding support 
As these two instructions in AVX extension are privileged instructions for
special purpose, it's only expected to be used in inlined assembly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-11 04:52:28 +00:00
Kay Tiong Khoo
c92cc5d918 fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test cases 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-10 21:52:25 +00:00
Kevin Enderby
12dccaed9c Fixes disassembler crashes on 2013 Haswell RTM instructions. 
rdar://13318048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-11 21:17:13 +00:00
Kay Tiong Khoo
951d361c28 death to extra whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175200 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 19:15:14 +00:00
Kay Tiong Khoo
7b672ed380 added basic support for Intel ADX instructions 
-feature flag, instructions definitions, test cases

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 19:08:21 +00:00
Benjamin Kramer
1386e9b7b1 Add intrinsics, code gen, assembler and disassembler support for the SSE4a extrq and insertq instructions. 
This required light surgery on the assembler and disassembler
because the instructions use an uncommon encoding. They are
the only two instructions in x86 that use register operands
and two immediates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157634 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-29 19:05:25 +00:00
Craig Topper
e45cddfa08 Add the tests that were supposed to go with r153935 that I forgot svn add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154165 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-04-06 07:09:59 +00:00