6 Commits

Author	SHA1	Message	Date
Jakob Stoklund Olesen	feaf34758a	Fix a bunch of ARM tests to be register allocation independent. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130800 91177308-0d34-0410-b5e6-96231b3b80d8	2011-05-03 22:31:21 +00:00
Evan Cheng	0c1aec1891	bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121746 91177308-0d34-0410-b5e6-96231b3b80d8	2010-12-14 03:22:07 +00:00
Evan Cheng	a9688c4b57	(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121606 91177308-0d34-0410-b5e6-96231b3b80d8	2010-12-11 04:11:38 +00:00
Jim Grosbach	9ce75625eb	Update tests to handle MC-inst instruction printing of shift operations. The ... legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic is correct and preferred according the ARM documentation (A8.6.98). The former are pseudo-instructions for the latter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114221 91177308-0d34-0410-b5e6-96231b3b80d8	2010-09-17 21:58:46 +00:00
Jim Grosbach	5423856e44	Add combiner patterns to more effectively utilize the BFI (bitfield insert) ... instruction for non-constant operands. This includes the case referenced in the README.txt regarding a bitfield copy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108608 91177308-0d34-0410-b5e6-96231b3b80d8	2010-07-17 03:30:54 +00:00
Jim Grosbach	469bbdb597	Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction ... and a combine pattern to use it for setting a bit-field to a constant value. More to come for non-constant stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108570 91177308-0d34-0410-b5e6-96231b3b80d8	2010-07-16 23:05:05 +00:00