Commit Graph

2799 Commits

Author SHA1 Message Date
Mohit K. Bhakkad
b284d4ae31 test commit (spelling correction)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223758 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-09 06:31:07 +00:00
Daniel Sanders
b856112d87 [mips] Add Mips-specific CCIf's for accessing the MipsCCState. NFC.
Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6213

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-08 15:40:09 +00:00
Matt Arsenault
459e595697 Allow target to specify prefix for labels
Use the MCAsmInfo instead of the DataLayout, and allow
specifying a custom prefix for labels specifically. HSAIL
requires that labels begin with @, but global symbols with &.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223323 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-04 00:06:57 +00:00
Daniel Sanders
d69ec73a46 [mips] Fix passing of small structures for big-endian O32.
Summary:
Like N32/N64, they must be passed in the upper bits of the register.

The new code could be merged with the existing if-statements but I've
refrained from doing this since it will make porting the O32 implementation
to tablegen harder later.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6463


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223148 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-02 20:40:27 +00:00
Vladimir Medic
462763dc0b The andi16, addiusp and jraddiusp micromips instructions were missing dedicated decoder methods in MipsDisassembler.cpp to properly decode immediate operands. These methods are added together with corresponding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223006 91177308-0d34-0410-b5e6-96231b3b80d8
2014-12-01 11:12:04 +00:00
Jozef Kolek
b087448a5f [mips][microMIPS] Implement NOP aliases
This patch implements microMIPS 16-bit (MOVE16 $0, $0) and
32-bit (SLL $0, $0, 0) NOP aliases.

http://reviews.llvm.org/D6440


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222953 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-29 13:29:24 +00:00
Zoran Jovanovic
7dc6143a82 [mips][microMIPS] Implement SWM16 and LWM16 instructions
Differential Revision: http://reviews.llvm.org/D5579


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222901 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 18:28:59 +00:00
Jozef Kolek
13fbabb7c8 [mips][microMIPS] Implement BREAK16 and SDBBP16 instructions
Patch by Radovan Obradovic.

Differential Revision: http://reviews.llvm.org/D5048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 18:18:42 +00:00
Daniel Sanders
68de93c3b4 [mips] Add synci instruction.
Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 17:28:10 +00:00
Jozef Kolek
2b8e58cc82 [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5
Differential Revision: http://reviews.llvm.org/D6419


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 14:41:44 +00:00
Jozef Kolek
832e2301cd [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16
Differential Revision: http://reviews.llvm.org/D6405


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 18:56:38 +00:00
Craig Topper
c0dae440e6 Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222801 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 00:46:26 +00:00
Zoran Jovanovic
137c475805 [mips][micromips] Use call instructions with short delay slots
Differential Revision: http://reviews.llvm.org/D6338


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 10:50:00 +00:00
Jozef Kolek
c19526770e [mips][microMIPS] Fix JRADDIUSP instruction
Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.

Differential Revision: http://reviews.llvm.org/D6365


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 16:14:10 +00:00
Jozef Kolek
b955bed064 [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions
Differential Revision: http://reviews.llvm.org/D5122


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:39:13 +00:00
Jozef Kolek
d49e74eaa5 [mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0
Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.

Differential Revision: http://reviews.llvm.org/D5780


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222652 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:25:53 +00:00
Jozef Kolek
18700de8fc [mips][microMIPS] Implement disassembler support for 16-bit instructions
With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.

Differential Revision: http://reviews.llvm.org/D6149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222648 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 13:29:59 +00:00
Jozef Kolek
d9accc1e5f [mips][microMIPS] This patch implements functionality in MIPS delay slot
filler such as if delay slot filler have to put NOP instruction into the
delay slot of microMIPS BEQ or BNE instruction which uses the register $0,
then instead of emitting NOP this instruction is replaced by the corresponding
microMIPS compact branch instruction, i.e. BEQZC or BNEZC.

Differential Revision: http://reviews.llvm.org/D3566


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222580 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-21 22:04:35 +00:00
Craig Topper
e0ed7df6b0 Remove a bunch of unnecessary typecasts to 'const TargetRegisterClass *'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222509 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-21 05:58:21 +00:00
Reid Kleckner
9c390888f7 Fix more instances of -Wsentinel on Windows with s/NULL/nullptr/
Follow up to r221940, where I must not have caught em all. NFC

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222481 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-20 23:51:47 +00:00
Reid Kleckner
d12434058d Add out of line virtual destructors to all LLVMTargetMachine subclasses
These recently all grew a unique_ptr<TargetLoweringObjectFile> member in
r221878.  When anyone calls a virtual method of a class, clang-cl
requires all virtual methods to be semantically valid. This includes the
implicit virtual destructor, which triggers instantiation of the
unique_ptr destructor, which fails because the type being deleted is
incomplete.

This is just part of the ongoing saga of PR20337, which is affecting
Blink as well. Because the MSVC ABI doesn't have key functions, we end
up referencing the vtable and implicit destructor on any virtual call
through a class. We don't actually end up emitting the dtor, so it'd be
good if we could avoid this unneeded type completion work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222480 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-20 23:37:18 +00:00
Zoran Jovanovic
d67cd80220 [mips][micromips] Implement SWM32 and LWM32 instructions
Differential Revision: http://reviews.llvm.org/D5519


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 16:44:02 +00:00
Jozef Kolek
9fece51399 [mips][microMIPS] Fix opcodes of MFHC1 and MTHC1 instructions.
Differential Revision: http://reviews.llvm.org/D6169


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 13:37:51 +00:00
Jozef Kolek
e4e84b22fe [mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.
Differential Revision: http://reviews.llvm.org/D5800


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222352 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 13:23:58 +00:00
Jozef Kolek
5c6c7e3295 [mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.
Differential Revision: http://reviews.llvm.org/D5799


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222351 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 13:11:09 +00:00
Jozef Kolek
43ae00e4e0 [mips][microMIPS] Implement LWXS instruction.
Differential Revision: http://reviews.llvm.org/D5407


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222348 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 11:39:12 +00:00
Jozef Kolek
baf97d8987 [mips][microMIPS] Implement SDBBP and RDHWR instructions.
Differential Revision: http://reviews.llvm.org/D5240


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222347 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 11:25:50 +00:00
David Blaikie
5401ba7099 Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool>
This is to be consistent with StringSet and ultimately with the standard
library's associative container insert function.

This lead to updating SmallSet::insert to return pair<iterator, bool>,
and then to update SmallPtrSet::insert to return pair<iterator, bool>,
and then to update all the existing users of those functions...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222334 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-19 07:49:26 +00:00
Jozef Kolek
c8ec320371 Test commit to verify that commit access works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222244 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-18 19:20:34 +00:00
Reid Kleckner
4f3c9858e0 Fix build of Mips code with MSVC by using our macro instead of __attribute__((unused)) directly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221956 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-14 00:39:33 +00:00
Reed Kotler
198bb22754 First stage of call lowering for Mips fast-isel
Summary:
This has most of what is needed for mips fast-isel call lowering for O32.
What is missing I will add on the next patch because this patch is already too large.
It should not be doing anything wrong but it will punt on some cases that it is basically
capable of doing.

The mechanism is there for parameters to be passed on the stack but I have not enabled it because it serves as a way for now to prevent some of the strange cases of O32 register passing that I have not fully checked yet and have some issues.

The Mips O32 abi rules are very complicated as far how data is passed in floating and integer registers.

However there is a way to think about this all very simply and this implementation reflects that.

Basically, the ABI rules are written as if everything is passed on the stack and aligned as such.
Once that is conceptually done, it is nearly trivial to reassign those locations to registers and
then all the complexity disappears.

So I have told tablegen that all the data is passed on the stack and during the lowering I fix
this by assigning to registers as per the ABI doc.

This has been my approach and you can line up what I did with the ABI document and see 1 to 1 what
is going on.



Test Plan: callabi.ll

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: jholewinski, echristo, ahatanak, llvm-commits, rfuhler

Differential Revision: http://reviews.llvm.org/D5714

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221948 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-13 23:37:45 +00:00
Aditya Nandakumar
365df40768 We can get the TLOF from the TargetMachine - so constructor no longer requires TargetLoweringObjectFile to be passed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221926 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-13 21:29:21 +00:00
Aditya Nandakumar
847729d19a This patch changes the ownership of TLOF from TargetLoweringBase to TargetMachine so that different subtargets could share the TLOF effectively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221878 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-13 09:26:31 +00:00
Zoran Jovanovic
cb5fadfe6a [mips][micromips] Add predicate 'InMicroMips' at CodeGen patterns for microMIPS instructions
Differential Revision: http://reviews.llvm.org/D6198


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221780 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-12 13:30:10 +00:00
Rafael Espindola
6a222ec893 Pass an ArrayRef to MCDisassembler::getInstruction.
With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t>
instead of a MemoryObject.

Even on X86 there is a maximum size an instruction can have. Given
that, it seems way simpler and more efficient to just pass an ArrayRef
to the disassembler instead of a MemoryObject and have it do a virtual
call every time it wants some extra bytes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221751 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-12 02:04:27 +00:00
Vasileios Kalintiris
328bc2f89e [mips] Add preliminary support for the MIPS II target.
Summary:
This patch enables code generation for the MIPS II target. Pre-Mips32
targets don't have the MUL instruction, so we add the correspondent
pattern that uses the MULT/MFLO combination in order to retrieve the
product.

This is WIP as we don't support code generation for select nodes due to
the lack of conditional-move instructions.

Reviewers: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6150

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221686 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-11 11:43:55 +00:00
Vasileios Kalintiris
b001cb6423 [mips] Add hardware register name "hwr_ulr" ($29)
The canonical name when printing assembly is still $29. The reason is that
GAS does not accept "$hwr_ulr" at the moment.

This addresses the comments from r221307, which reverted the original
commit r221299.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221685 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-11 11:22:39 +00:00
Vasileios Kalintiris
d3da72c5b3 Recommit "[mips] Add names and tests for the hardware registers"
The original commit r221299 was reverted in r221307.  I removed the name
"hrw_ulr" ($29) from the original commit because two tests were failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221681 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-11 10:31:31 +00:00
Rafael Espindola
9272305648 MCAsmParserExtension has a copy of the MCAsmParser. Use it.
Base classes were storing a second copy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221667 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-11 05:18:41 +00:00
Rafael Espindola
d342c4c748 Misc style fixes. NFC.
This fixes a few cases of:

* Wrong variable name style.
* Lines longer than 80 columns.
* Repeated names in comments.
* clang-format of the above.

This make the next patch a lot easier to read.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221615 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-10 18:11:10 +00:00
Zoran Jovanovic
c63c935a80 [mips][microMIPS] Fix issue with delay slot filler and microMIPS
Differential Revision: http://reviews.llvm.org/D6193


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221612 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-10 17:27:56 +00:00
Daniel Sanders
62c2faa216 [mips] Fix sret arguments for N32/N64 which were accidentally broken in r221534.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221604 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-10 15:57:53 +00:00
Daniel Sanders
fe2b8b1960 [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit structs...
Summary:
... and after all that refactoring, it's possible to distinguish softfloat
floating point values from integers so this patch no longer breaks softfloat to
do it.

Remove direct handling of i32's in the N32/N64 ABI by promoting them to
i64. This more closely reflects the ABI documentation and also fixes
problems with stack arguments on big-endian targets.

We now rely on signext/zeroext annotations (already generated by clang) and
the Assert[SZ]ext nodes to avoid the introduction of unnecessary sign/zero
extends.

It was not possible to convert three tests to use signext/zeroext. These tests
are bswap.ll, ctlz-v.ll, ctlz-v.ll. It's not possible to put signext on a
vector type so we just accept the sign extends here for now. These tests don't
pass the vectors the same way clang does (clang puts multiple elements in the
same argument, these map 1 element to 1 argument) so we don't need to worry too
much about it.

With this patch, all known N32/N64 bugs should be fixed and we now pass the
first 10,000 tests generated by ABITest.py.

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221534 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-07 16:54:21 +00:00
Daniel Sanders
01657f390d [mips] Removed the remainder of MipsCC. NFC.
Summary:
One of the calls to AllocateStack (the one in LowerCall) doesn't look like
it should be there but it was there before and removing it breaks the
frame size calculation.

Reviewers: vmedic, theraven

Reviewed By: theraven

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6116

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221529 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-07 15:33:08 +00:00
Daniel Sanders
46c098238e [mips] Remove MipsCC::reservedArgArea() in favour of MipsABIInfo::GetCalleeAllocdArgSizeInBytes(). NFC.
Summary:

Reviewers: theraven, vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6115


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221528 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-07 15:03:53 +00:00
NAKAMURA Takumi
490119e467 MipsCCState.h: Use LLVM_DELETED_FUNCTION for msc17.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221527 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-07 14:56:31 +00:00
Daniel Sanders
6b846945ec [mips] Move MipsCCState to a separate file and clang-formatted it.
Summary: Depends on D6113

Reviewers: theraven, vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6114

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221525 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-07 14:24:31 +00:00
Daniel Sanders
7fc57f4cef [mips] Fix unused variable warnings introduced in r221521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-07 12:43:01 +00:00
Daniel Sanders
605a80b218 [mips] Remove remaining use of MipsCC::intArgRegs() in favour of MipsABIInfo::GetByValArgRegs() and MipsABIInfo::GetVarArgRegs()
Summary: Depends on D6112

Reviewers: theraven, vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6113

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221521 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-07 12:21:37 +00:00
Daniel Sanders
73bbfc537e [mips] Remove MipsCC::getRegVT(). NFC
Summary: It's no longer used.

Reviewers: vmedic, theraven

Reviewed By: theraven

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6112

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221519 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-07 12:02:59 +00:00