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Author SHA1 Message Date
Frits van Bommel
26e097ca4b Teach jump threading to "look through" a select when the branch direction of a terminator depends on it. 
When it sees a promising select it now tries to figure out whether the condition of the select is known in any of the predecessors and if so it maps the operands appropriately.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 09:51:20 +00:00
Bill Wendling
22447ae54b Add fixups for Thumb LDR/STR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121858 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 08:51:02 +00:00
Rafael Espindola
2bf6afc277 Relax alignment fragments. 
With this we don't need the EffectiveSize field anymore. Without that field
LayoutFragment only updates offsets and we don't need to invalidate the
current fragment when it is relaxed (only the ones following it).

This is also a very small improvement in the accuracy of the layout info as
we now use the after relaxation size immediately.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121857 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 08:45:53 +00:00
Rafael Espindola
f9a4476173 Patch by David Meyer to avoid a O(N^2) behaviour when relaxing fragments. 
Since we now don't update addresses so early, we might relax a bit more than
we need to. This is simillar to the issue in PR8467.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121856 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 07:39:29 +00:00
Chris Lattner
9448184b99 add another overflow idiom 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121854 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 07:28:58 +00:00
Chris Lattner
08859ffa63 add a note about overflow idiom recognition. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121853 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 07:25:55 +00:00
Rafael Espindola
b35d56c2fe Generalize an assert. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121851 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 07:12:24 +00:00
Chris Lattner
ef17f08dbc add a shift/imul missed optimization 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121850 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 07:10:43 +00:00
Chris Lattner
2fc36e19b1 add a note about a SPEC hack that gcc mainline does. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121849 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 06:38:24 +00:00
Chris Lattner
33e77d3cb9 take care of some todos, transforming [us]mul_lohi into 
a wider mul if the wider mul is legal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121848 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 06:04:19 +00:00
Chris Lattner
2ff28e4b9e merge two tests 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121847 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 05:58:59 +00:00
Chris Lattner
1a0fbe2cf4 when transforming a MULHS into a wider MUL, there is no need to SRA the 
result, the top bits are truncated off anyway, just use SRL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121846 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 05:51:39 +00:00
Chris Lattner
ba3c815570 make qsort predicate more conformant by returning 0 for equal values. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121838 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 04:52:41 +00:00
Chris Lattner
9c6b60eb28 various cleanups to tblgen, patch by Garrison Venn! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121837 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 04:48:22 +00:00
Bill Wendling
f722699f8a Add mention that we support FreeBSD/amd64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121832 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:35:55 +00:00
Kevin Enderby
53ef11884f Add some more MC tests for ARM arithmetic instructions that update or don't 
update the condition codes.  These come from my test generator and are just
the ones that MC currently assembles correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121830 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:24:36 +00:00
Mikhail Glushenkov
24d7fa2b6e Copy-pastos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121829 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:22:34 +00:00
Mikhail Glushenkov
36604a60e8 Remove ConvertToMAttrImpl, it became too '-march'-specific. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121828 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:22:29 +00:00
Mikhail Glushenkov
42db997688 llvmc: Support -march arguments that should be forwarded to llc as -mcpu. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121827 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:22:25 +00:00
Mikhail Glushenkov
2ac7eb8c61 llvmc: Better -mfpu/-mcpu support for ARM & PPC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121826 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:22:20 +00:00
Mikhail Glushenkov
26e10aeaf4 llvmc: more complete -march table for ARM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121825 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:22:15 +00:00
Mikhail Glushenkov
73e78098fd llvmc: Support -mabi/-mfloat-abi. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121824 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:22:10 +00:00
Mikhail Glushenkov
bebea87284 llvmc: Forward -march/-mcpu/-mtune to as & ld. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121823 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:22:05 +00:00
Mikhail Glushenkov
87685e8e8f llvmc: make switch options ZeroOrMore by default. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121822 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:21:59 +00:00
Bill Wendling
bc4224bc6b Reapply r121808 now that the missing patterns have been supplied. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121820 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 01:03:19 +00:00
Bill Wendling
415af3452e Add some missing patterns now that tLDRB and tLDRH are split into reg and 
immediate versions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121819 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 00:58:57 +00:00
Owen Anderson
86e8a700f5 Fix PR8790, another instance where unreachable code can cause instruction simplification to fail, 
this case involve a select that simplifies to itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121817 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 00:55:35 +00:00
Owen Anderson
93f83deba1 Cleanup trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121816 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 00:52:44 +00:00
Bill Wendling
7d1d8db54a Revert r121808 until I can fix the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121815 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-15 00:04:00 +00:00
Jim Grosbach
9d04dc52a5 thumb adr fixup needs alignment just like the t2 version. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121812 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:47:35 +00:00
Bill Wendling
345cdb6475 Comments and cleaning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121809 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:42:48 +00:00
Bill Wendling
2af0fd3fee Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In 
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121808 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:40:49 +00:00
Jakob Stoklund Olesen
257c556d85 Simplify RegAllocGreedy's use of register aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121807 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:38:19 +00:00
Jakob Stoklund Olesen
eb7464ebda Simplify CCState's use of register aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121806 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:28:01 +00:00
Jakob Stoklund Olesen
597faa8f1f Simplify AggressiveAntiDepBreaker's use of register aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121805 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:23:15 +00:00
Jakob Stoklund Olesen
16999da951 Simplyfy RegAllocBasic by using getOverlaps instead of getAliasSet. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121801 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:10:48 +00:00
Jakob Stoklund Olesen
b83ff84193 Introduce TargetRegisterInfo::getOverlaps(Reg), returning a list of all 
registers that alias Reg, including itself. This is almost the same as the
existing getAliasSet() method, except for the inclusion of Reg.

The name matches the reflexive TRI::regsOverlap(x, y) relation.

It is very common to do stuff to a register and all its aliases:

  stuff(Reg)
  for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias)
    stuff(*Alias);

That can now be written as the simpler:

  for (const unsigned *Alias = TRI->getOverlaps(Reg); *Alias; ++Alias)
    stuff(*Alias);

This change requires a bit more constant space for the alias lists because Reg
is included and because the empty alias list cannot be shared any longer.

If the getAliasSet method is eventually removed, this space can be reclaimed by
sharing overlap lists. For instance, %rax and %eax have identical overlap sets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121800 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 23:03:42 +00:00
Jim Grosbach
d40963c406 Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:28:03 +00:00
Bill Wendling
ee2b350d83 Fix comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121797 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:26:49 +00:00
Bill Wendling
b6faf65215 Multiclassify the LDR/STR encoding patterns. The only functionality difference 
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121794 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 22:10:49 +00:00
Evan Cheng
bbc726d624 Fix a minor bug in two-address pass. It was missing a commute opportunity. 
regB = move RCX
regA = op regB, regC
RAX  = move regA
where both regB and regC are killed. If regB is constrainted to non-compatible
physical registers but regC is not constrainted at all, then it's better to
commute the instruction.
       movl    %edi, %eax
       shlq    $32, %rcx
       leaq    (%rcx,%rax), %rax
=>
       movl    %edi, %eax
       shlq    $32, %rcx
       orq     %rcx, %rax
rdar://8762995


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121793 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 21:34:53 +00:00
Jim Grosbach
8d6d7d6e30 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121792 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 21:28:29 +00:00
Matt Beaumont-Gay
3ef9f3da39 Move debugging code entirely within DEBUG(). Silences an unused variable 
warning in the opt build.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121791 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 21:14:55 +00:00
Jim Grosbach
40edf73a62 Refactor a bit for legibility. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121790 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 21:10:47 +00:00
Jim Grosbach
00f25fa43e trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121789 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 20:46:39 +00:00
Jim Grosbach
eb61272150 Make sure to propagate the predicate operands for LEApcrel to ADR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121788 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 20:45:47 +00:00
Owen Anderson
86abd48fd0 Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121784 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 19:42:53 +00:00
Jakob Stoklund Olesen
bfce678de7 Add LiveIntervalUnion print methods, RegAllocGreedy::trySplit debug spew. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121783 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 19:38:49 +00:00
Jakob Stoklund Olesen
4a84cce3ed Use TRI::printReg instead of AbstractRegisterDescription when printing 
LiveIntervalUnions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121781 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 18:53:47 +00:00
Jakob Stoklund Olesen
414e5023f8 Add TargetRegisterInfo::printReg() to pretty-print registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121780 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-12-14 18:53:39 +00:00