and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
targets to register custom legalizers for ConstantFP in case there isn't a
fixed list of constants that can be generated. On some architectures (ia64?)
all fp immediates are legal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25769 91177308-0d34-0410-b5e6-96231b3b80d8
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25222 91177308-0d34-0410-b5e6-96231b3b80d8
packed types with an element count of 1, although more generic support is
coming. This allows LLVM to turn the following code:
void %foo(<1 x float> * %a) {
entry:
%tmp1 = load <1 x float> * %a;
%tmp2 = add <1 x float> %tmp1, %tmp1
store <1 x float> %tmp2, <1 x float> *%a
ret void
}
Into:
_foo:
lfs f0, 0(r3)
fadds f0, f0, f0
stfs f0, 0(r3)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24416 91177308-0d34-0410-b5e6-96231b3b80d8
this and have it in about the same form, I think this makes sense.
on X86, you do a RDTSC (64bit result, from any ring since the P5MMX)
on Alpha, you do a RDCC
on PPC, there is a sequence which may or may not work depending on how things
are setup by the OS. Or something like that. Maybe someone who knows PPC
can add support. Something about the time base register.
on Sparc, you read %tick, which in some solaris versions (>=8) is readable by
userspace
on IA64 read ar.itc
So I think the ulong is justified since all of those are 64bit.
Support is slighly flaky on old chips (P5 and lower) and sometimes
depends on OS (PPC, Sparc). But for modern OS/Hardware (aka this decade),
we should be ok.
I am still not sure what to do about lowering. I can either see a lower to 0, to
gettimeofday (or the target os equivalent), or loudly complaining and refusing to
continue.
I am commiting an Alpha implementation. I will add the X86 implementation if I
have to (I have use of it in the near future), but if someone who knows that
backend (and the funky multi-register results) better wants to add it, it would
take them a lot less time ;)
TODO: better lowering and legalizing, and support more platforms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24299 91177308-0d34-0410-b5e6-96231b3b80d8
This eliminates the vector, allows constant time removal of a node from
a graph, and makes iteration over the all nodes list stable when adding
nodes to the graph.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24262 91177308-0d34-0410-b5e6-96231b3b80d8
allocated. Further, in the common case where a node has a single value, just
reference an element from a small array. This is a small compile-time wi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24250 91177308-0d34-0410-b5e6-96231b3b80d8
This saves 12 bytes from SDNode, but doesn't speed things up substantially
(our graphs apparently already fit within the cache on my g5). In any case
this reduces memory usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24248 91177308-0d34-0410-b5e6-96231b3b80d8
registers, and the incoming values have already been zero or sign extended
from the appopriate type to the register width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23146 91177308-0d34-0410-b5e6-96231b3b80d8
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23081 91177308-0d34-0410-b5e6-96231b3b80d8
is greater than the range of building selection dag node types, and
getTargetOpcode(), which returns the node opcode less the value of
isd::builtin_op_end, which specifies the end of the builtin types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22844 91177308-0d34-0410-b5e6-96231b3b80d8
