Commit Graph

177 Commits

Author SHA1 Message Date
Adam Nemet
b1f410a35b [X86] Increase X86_MAX_OPERANDS from 5 to 6
This controls the number of operands in the disassembler's x86OperandSets
table.  The entries describe how the operand is encoded and its type.

Not to surprisingly 5 operands is insufficient for AVX512.  Consider
VALIGNDrrik in the next patch.  These are its operand specifiers:

  { /* 328 */
    { ENCODING_DUP, TYPE_DUP1 },
    { ENCODING_REG, TYPE_XMM512 },
    { ENCODING_WRITEMASK, TYPE_VK8 },
    { ENCODING_VVVV, TYPE_XMM512 },
    { ENCODING_RM_CD64, TYPE_XMM512 },
    { ENCODING_IB, TYPE_IMM8 },
  },

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214889 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-05 17:23:01 +00:00
Rafael Espindola
34c5b5b952 Finish inverting the MC -> Object dependency.
There were still some disassembler bits in lib/MC, but their use of Object
was only visible in the includes they used, not in the symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213808 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-23 22:26:07 +00:00
Robert Khasanov
aac33cfc08 [SKX] Enabling SKX target and AVX512BW, AVX512DQ, AVX512VL features.
Enabling HasAVX512{DQ,BW,VL} predicates.
Adding VK2, VK4, VK32, VK64 masked register classes.
Adding new types (v64i8, v32i16) to VR512.
Extending calling conventions for new types (v64i8, v32i16)

Patch by Zinovy Nis <zinovy.y.nis@intel.com>
Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213545 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-21 14:54:21 +00:00
Adam Nemet
6ae2941874 [X86] AVX512: Add disassembler support for compressed displacement
There are two parts here.  First is to modify tablegen to adjust the encoding
type ENCODING_RM with the scaling factor.

The second is to use the new encoding types to compute the correct
displacement in the decoder.

Fixes <rdar://problem/17608489>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213281 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-17 17:04:56 +00:00
Adam Nemet
f36c3de849 [Disasm][AVX512] Implement decoding of top bit for non-destructive reg fields
V' bit in the P2 byte of the EVEX prefix provides the top bit of the NDD and
NDS register fields.  This was simply not used in the decoder until now.

Fixes <rdar://problem/17402661>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211565 91177308-0d34-0410-b5e6-96231b3b80d8
2014-06-24 01:42:32 +00:00
Patrik Hagglund
696bbc59ae Fix gcc -Wsign-compare warning in X86DisassemblerTables.cpp.
X86_MAX_OPERANDS is changed to unsigned.

Also, add range-based for loops for affected loops. This in turn
needed an ArrayRef instead of a pointer-to-array in
InternalInstruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207413 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 12:12:27 +00:00
Craig Topper
c34a25d59d [C++] Use 'nullptr'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207394 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 04:05:08 +00:00
Craig Topper
c848b1bbcf [C++] Use 'nullptr'. Target edition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207197 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-25 05:30:21 +00:00
Elena Demikhovsky
3890a42255 X86Disassembler - fixed a bug in immediate print
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206953 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-23 07:21:04 +00:00
Chandler Carruth
58f58c97f0 [cleanup] Lift using directives, DEBUG_TYPE definitions, and even some
system headers above the includes of generated '.inc' files that
actually contain code. In a few targets this was already done pretty
consistently, but it wasn't done *really* consistently anywhere. It is
strictly cleaner IMO and necessary in a bunch of places where the
DEBUG_TYPE is referenced from the generated code. Consistency with the
necessary places trumps. Hopefully the build bots are OK with the
movement of intrin.h...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206838 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-22 02:03:14 +00:00
Chandler Carruth
283b399377 [Modules] Make Support/Debug.h modular. This requires it to not change
behavior based on other files defining DEBUG_TYPE, which means it cannot
define DEBUG_TYPE at all. This is actually better IMO as it forces folks
to define relevant DEBUG_TYPEs for their files. However, it requires all
files that currently use DEBUG(...) to define a DEBUG_TYPE if they don't
already. I've updated all such files in LLVM and will do the same for
other upstream projects.

This still leaves one important change in how LLVM uses the DEBUG_TYPE
macro going forward: we need to only define the macro *after* header
files have been #include-ed. Previously, this wasn't possible because
Debug.h required the macro to be pre-defined. This commit removes that.
By defining DEBUG_TYPE after the includes two things are fixed:

- Header files that need to provide a DEBUG_TYPE for some inline code
  can do so by defining the macro before their inline code and undef-ing
  it afterward so the macro does not escape.

- We no longer have rampant ODR violations due to including headers with
  different DEBUG_TYPE definitions. This may be mostly an academic
  violation today, but with modules these types of violations are easy
  to check for and potentially very relevant.

Where necessary to suppor headers with DEBUG_TYPE, I have moved the
definitions below the includes in this commit. I plan to move the rest
of the DEBUG_TYPE macros in LLVM in subsequent commits; this one is big
enough.

The comments in Debug.h, which were hilariously out of date already,
have been updated to reflect the recommended practice going forward.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206822 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 22:55:11 +00:00
NAKAMURA Takumi
3c390e5184 Appease autoconf build since X86Disassembler.c has been disappeared in r206717.
It can be reverted a few days later, after X86Disassembler.d is updated not to contain "X86Disassembler.c".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206758 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-21 14:59:11 +00:00
Richard Smith
f8107eb051 C++ has a bool type! (And C's had one too, for 15 years...)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206723 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-20 22:15:37 +00:00
Richard Smith
4c09131c4f More C++ification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-20 22:10:16 +00:00
Richard Smith
5c1b738d96 Remove some more C junk from these files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206721 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-20 21:56:02 +00:00
Richard Smith
6f37488863 Don't provide two different definitions of ModRMDecision, OpcodeDecision, and ContextDecision in different source files (depending on #define magic).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206720 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-20 21:52:16 +00:00
Richard Smith
5aacafc256 Don't define llvm::X86Disassembler::InstructionSpecifier in different ways in
different source files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206719 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-20 21:35:26 +00:00
Richard Smith
4b35598496 Maybe if I touch this file the buildbots will actually rerun configure like they need to...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206718 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-20 21:28:33 +00:00
Richard Smith
fe0e7bb571 What year is it! This file has no reason to be written in C, and has doubly no
reason to expose a global symbol 'decodeInstruction' nor to pollute the global
scope with a bunch of external linkage entities (some of which conflict with
others elsewhere in LLVM).

This is just the initial transition to C++; more cleanups to follow.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206717 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-20 21:07:34 +00:00
Lang Hames
508bd63046 [MC] Require an MCContext when constructing an MCDisassembler.
This patch re-introduces the MCContext member that was removed from
MCDisassembler in r206063, and requires that an MCContext be passed in at
MCDisassembler construction time. (Previously the MCContext member had been
initialized in an ad-hoc fashion after construction). The MCCContext member
can be used by MCDisassembler sub-classes to construct constant or
target-specific MCExprs.

This patch updates disassemblers for in-tree targets, and provides the
MCRegisterInfo instance that some disassemblers were using through the
MCContext (previously those backends were constructing their own
MCRegisterInfo instances).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206241 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-15 04:40:56 +00:00
Lang Hames
4e510c10b5 [X86] unique_ptr'ify one of X86GenericDisassembler's members.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206127 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-13 04:09:16 +00:00
Craig Topper
badf4cb75a [X86] Check return value of readSIB in disassembler so errors propagate. In particular this makes a too short instruction with a missing SIB byte fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204305 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-20 05:56:00 +00:00
Craig Topper
124c86ee4a [C++11] Add 'override' keyword to virtual methods that override their base class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-09 18:03:14 +00:00
Yaron Keren
7bc835b7bf Cleaning up two more pre-Visual C++ 2012 build hacks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203093 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-06 08:05:43 +00:00
Craig Topper
82a644adf2 Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201641 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-19 05:34:21 +00:00
Craig Topper
3457506fb9 Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201507 91177308-0d34-0410-b5e6-96231b3b80d8
2014-02-17 10:03:43 +00:00
Alp Toker
fdfcf71598 Avoid C++ comment in C sources
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c:1361:7: error: C++ style comments are not allowed in ISO C90

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200153 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-26 18:44:34 +00:00
Craig Topper
c45addd6e4 Set displacementSize to 1 for instrucitons with mod==0x1. Fixes PR17310. Modified from patch by James Courtier-Dutton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200100 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-25 22:48:43 +00:00
Alp Toker
ae43cab6ba Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-24 17:20:08 +00:00
NAKAMURA Takumi
f9e66a412b X86Disassembler.cpp: Fix @param introduced in r199804. [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199855 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-23 00:37:25 +00:00
Benjamin Kramer
7dd91217c7 Remove param doxygen comment for non-existing parameter.
Found by -Wdocumentation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199814 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 16:22:17 +00:00
David Woodhouse
b92c3984b2 [x86] Fix uninitialized variable warning in translate{Src,Dst}Index
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199811 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:31:29 +00:00
David Woodhouse
ccbfd5b18a [x86] Allow address-size overrides for STOS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199804 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:21 +00:00
David Woodhouse
db9fa461d7 [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199803 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-22 15:08:08 +00:00
David Woodhouse
9334b07527 [x86] Fix disassembly of MOV16ao16 et al.
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199654 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 12:02:53 +00:00
David Woodhouse
a3fb0f9773 [x86] Fix 16-bit disassembly of JCXZ/JECXZ
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199653 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 12:02:48 +00:00
David Woodhouse
7360e8caa3 [x86] Fix 16-bit handling of OpSize bit
When disassembling in 16-bit mode the meaning of the OpSize bit is
inverted. Instructions found in the IC_OPSIZE context will actually
*not* have the 0x66 prefix, and instructions in the IC context will
have the 0x66 prefix. Make use of the existing special-case handling
for the 0x66 prefix being in the wrong place, to cope with this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199650 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 12:02:35 +00:00
David Woodhouse
e6f5bb99fc [x86] Infer disassembler mode from SubtargetInfo feature bits
Aside from cleaning up the code, this also adds support for the -code16
environment and actually enables the MODE_16BIT mode that was previously
not accessible.

There is no point adding any testing for 16-bit yet though; basically
nothing will work because we aren't handling the OpSize prefix correctly
for 16-bit mode.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-20 12:02:31 +00:00
Craig Topper
4b42f26ab5 VEX_PREFIX_66 doesn't need to set the hasOpSize flag since VEX instructions don't use the size fields it controls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-17 07:11:45 +00:00
Craig Topper
85026d9375 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 07:36:58 +00:00
David Woodhouse
aab59870a4 [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198759 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:58:24 +00:00
Craig Topper
5cfd40ccd4 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198284 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 21:52:57 +00:00
NAKAMURA Takumi
550848ecb9 X86Disassembler.cpp: Prune stray @return on translateFPRegister(). [-Wdocumentation]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198279 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 16:19:26 +00:00
Craig Topper
95a3ccdd80 Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198278 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 15:29:32 +00:00
Craig Topper
979b2cd2bc Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198276 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-01 14:22:37 +00:00
Craig Topper
5cbbd7e1a5 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 17:21:44 +00:00
Craig Topper
31b27056a6 Remove old comment referring to an argument that no longer exists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-31 15:29:14 +00:00
Craig Topper
e6d2dce7ab Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-30 19:16:48 +00:00
Elena Demikhovsky
09a63715ce AVX-512: decoder for AVX-512, made by Alexey Bader.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198013 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-25 11:40:51 +00:00
Elena Demikhovsky
376a81d8ce AVX-512: Added legal type MVT::i1 and VK1 register for it.
Added scalar compare VCMPSS, VCMPSD.
Implemented LowerSELECT for scalar FP operations.
I replaced FSETCCss, FSETCCsd with one node type FSETCCs.
Node extract_vector_elt(v16i1/v8i1, idx) returns an element of type i1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197384 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-16 13:52:35 +00:00