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2e4cd27799
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29266 Commits

Author SHA1 Message Date
Chad Rosier
2e4cd27799 [AArch64] Basic Sched Model for Cortex-A57. 
Patch by Dave Estes<cestes@codeaurora.org>
Differential Revision: http://reviews.llvm.org/D4008

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210705 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 21:06:56 +00:00
Tom Stellard
beef5c58d7 R600: Set correct InstrItinClass for instructions using *Helper classes 
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210703 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 20:51:42 +00:00
Tom Stellard
7ae77a1b1e R600: BCNT_INT is a vector only instruction 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210702 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 20:51:39 +00:00
Jim Grosbach
a542ff2804 ARM: honor hex immediate formatting for ldr/str i12 offsets. 
Previously we would always print the offset as decimal, regardless of
the formatting requested. Now we use the formatImm() helper so the value
is printed as the client (LLDB in the motivating example) requested.

Before:
ldr.w r8, [sp, #180] @ always

After:
ldr.w r8, [sp, #0xb4] @ when printing hex immediates
ldr.w r8, [sp, #0180] @ when printing decimal immediates

rdar://17237103

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210701 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 20:26:45 +00:00
Matt Arsenault
7fa80b45eb R600/SI: Fix bitcast between v2i32 and f64 
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210692 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 19:31:13 +00:00
Matt Arsenault
4600175c7f R600/SI: Update place using old subtarget predicate 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210683 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:11:34 +00:00
Matt Arsenault
c9dbd0da7a R600/SI: Add common 64-bit LDS atomics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210680 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:54 +00:00
Matt Arsenault
481a071a8b R600/SI: Add instruction definitions for 64-bit LDS atomics 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210679 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:50 +00:00
Matt Arsenault
6b19a3a474 R600/SI: Add 32-bit LDS atomic cmpxchg 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210678 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:48 +00:00
Matt Arsenault
a396a70c1d R600/SI: Use LDS atomic inc / dec 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210677 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:45 +00:00
Matt Arsenault
2da1a85cbb R600/SI: Add other LDS atomic operations 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210676 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:42 +00:00
Matt Arsenault
507d8cad7b R600/SI: Add instruction definitions for more LDS ops 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210675 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:39 +00:00
Matt Arsenault
4a19dd468d R600/SI: Fix backwards names for local atomic instructions. 
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210674 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:37 +00:00
Matt Arsenault
b97095b94f R600/SI: Refactor local atomics. 
Use patterns that will also match the immediate offset to
match the normal read / writes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210673 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 18:08:34 +00:00
Matt Arsenault
8a9df8f92c R600/SI: Use v_cvt_f32_ubyte* instructions 
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210666 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 17:50:44 +00:00
Matt Arsenault
a2dca4cc04 R600/SI: Fix selection failure on scalar_to_vector 
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210664 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 17:40:32 +00:00
Tim Northover
55c8ec6588 X86: add stringy name for X86ISD::LCMPXCHG16_DAG 
I don't know what "target specific node #383" is, and I don't want to
have to.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210663 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 17:04:08 +00:00
Matheus Almeida
6b3f3922bf [mips] Implement jr.hb and jalr.hb (Jump Register and Jump and Link Register with Hazard Barrier). 
Summary: These instructions are available in ISAs >= mips32/mips64. For mips32r6/mips64r6, jr.hb has a new encoding format.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4019

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210654 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 15:05:56 +00:00
Cameron McInally
998d8f50a7 Add AVX512 masked leadz instrinsic support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210652 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 12:54:45 +00:00
Andrea Di Biagio
a069e64112 [X86] Refactor the logic to select horizontal adds/subs to a helper function. 
This patch moves part of the logic implemented by the target specific
combine rules added at r210477 to a separate helper function.
This should make easier to add more rules for matching AVX/AVX2 horizontal
adds/subs.

This patch also fixes a problem caused by a wrong check performed on indices
of extract_vector_elt dag nodes in input to the scalar adds/subs.

New tests have been added to verify that we correctly check indices of
extract_vector_elt dag nodes when selecting a horizontal operation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210644 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 07:57:50 +00:00
Rafael Espindola
e12b0bbc02 Try to fix the msvc build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210636 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 04:41:37 +00:00
Matt Arsenault
3692045d8e Use cast instead of assert + dyn_cast 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210628 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 03:30:06 +00:00
Matt Arsenault
e0162b9648 R600: Add helper functions. 
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210627 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 03:29:54 +00:00
Eric Christopher
f68129838b Remove duplicate copy of InstrItineraryData from the TargetMachine, 
it's already on the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210619 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 00:53:17 +00:00
Eric Christopher
e290e4abc3 Move to a private function to initialize the subtarget dependencies 
so that we can use initializer lists for the AArch64 Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210616 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 00:46:34 +00:00
Eric Christopher
0166af890c Move to a private function to initialize the subtarget dependencies 
so that we can use initializer lists for the X86Subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210614 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 00:25:19 +00:00
Juergen Ributzka
0adbcf3ba9 [FastISel][X86] Extend support for {s|u}{add|sub|mul}.with.overflow intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210610 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 23:52:44 +00:00
Eric Christopher
9c84db6ba3 Use unique_ptr for X86Subtarget pointer members. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210606 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 23:26:47 +00:00
Eric Christopher
fe80185273 Move AArch64TargetLowering to AArch64Subtarget. 
This currently necessitates a TargetMachine for the TargetLowering
constructor and TLOF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210605 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 23:26:45 +00:00
Eric Christopher
159e408563 Move AArch64InstrInfo to AArch64Subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210599 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 22:57:25 +00:00
Eric Christopher
468a0ce16f Remove a method that was just replacing direct access to a member. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210598 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 22:57:21 +00:00
Eric Christopher
c6e5ff46be Remove the use of TargetMachine from X86InstrInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210596 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 22:34:31 +00:00
Eric Christopher
c72fe200ad Move X86RegisterInfo away from using the TargetMachine and only 
using the subtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210595 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 22:34:28 +00:00
Eric Christopher
f85ae2a8c2 Use the TargetMachine on the DAG or the MachineFunction instead 
of using the cached TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210589 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 21:25:13 +00:00
Tom Stellard
cd0b8d6cbf R600/SI: Emit an error when attempting to spill VGPRs v4 
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210588 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 21:20:41 +00:00
Tom Stellard
48d11b0228 R600/SI: Fix a crash when spilling SGPRs 
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210587 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 21:20:38 +00:00
Matt Arsenault
1f4772305a R600: Use BCNT_INT for evergreen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210569 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:28 +00:00
Matt Arsenault
69891c0115 R600/SI: Implement i64 ctpop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210568 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:24 +00:00
Matt Arsenault
ee9772d9dd R600/SI: Use bcnt instruction for ctpop 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210567 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:18:21 +00:00
Matt Arsenault
bfd00e21b7 R600: Handle fcopysign 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210564 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 19:00:20 +00:00
Matt Arsenault
0ba78a9121 R600/SI: Handle sign_extend and zero_extend to i64 with patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210563 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:54:59 +00:00
Eric Christopher
a1c71aa78d Add a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210559 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:31:18 +00:00
Eric Christopher
30ad4cb09b Move AArch64SelectionDAGInfo down to the subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210557 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:21:53 +00:00
Eric Christopher
75b55475bc Remove the cached little endian variable. We can get it easily off 
of the DataLayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210555 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:11:20 +00:00
Eric Christopher
b8dca33a05 Have AArch64SelectionDAGInfo take a DataLayout parameter rather 
than a TargetMachine.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210554 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:06:28 +00:00
Eric Christopher
e3a06bcd8a Remove caching of the subtarget for AArch64SelectionDAGInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210553 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:06:25 +00:00
Eric Christopher
fc0f6e8cc5 Move DataLayout onto the AArch64 subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210552 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 18:06:23 +00:00
Eric Christopher
c4f9370391 Move AArch64FrameLowering into the subtarget. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210549 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 17:44:12 +00:00
Eric Christopher
8128a7965f Remove the uses of AArch64TargetMachine and AArch64Subtarget from 
AArch64FrameLowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210548 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 17:33:39 +00:00
Reed Kotler
805c9e4943 Do Materialize Floating Point in Mips Fast-Isel 
Summary:
Implement materialize of floating point literals in Mips Fast-Isel

Reopened version of D3659

Test Plan: simplestorefp1.ll

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D4071

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210546 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-10 16:45:44 +00:00