Craig Topper
3daa5c29d4
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-30 07:09:35 +00:00
Kevin Enderby
fff64ca9cf
Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 22:06:28 +00:00
Craig Topper
8fd13b6de5
Fix disassembling of VCVTSD2SI
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138623 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-26 04:49:29 +00:00
Craig Topper
113061d39b
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 07:42:00 +00:00
Craig Topper
ea03659d23
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138551 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-25 06:57:46 +00:00
Craig Topper
e004d941ec
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138034 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-19 05:28:50 +00:00
Eli Friedman
7105259ce8
Make the disassembler able to disassemble a bunch of instructions with names in the TableGen files containing "64" on x86-32. This includes a bunch of x87 instructions, like fld, and a bunch of SSSE3 instructions on MMX registers like pshufb. Part of PR8873.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135337 91177308-0d34-0410-b5e6-96231b3b80d8
2011-07-16 02:41:28 +00:00
Sean Callanan
9a9d8b9732
Basic sanity checks to ensure that 2- and 3-byte
...
VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-15 01:32:46 +00:00
Sean Callanan
8fbc00b5ba
Fixed a bug in the enhanced disassembler that caused
...
it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126302 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-23 03:31:28 +00:00
Sean Callanan
ec243ae2b8
Added a testcase for the enhanced disassembly bug
...
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126182 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 02:19:18 +00:00
Rafael Espindola
2f867a63da
Correctly disassemble truncated asm.
...
Patch by Richard Simth.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122962 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-06 16:48:42 +00:00
Dale Johannesen
2ae2302abc
Segregate tests by target.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-14 18:14:32 +00:00
