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120 Commits

Author SHA1 Message Date
Zoran Jovanovic
9d115effdf [mips][microMIPS] Implement ERET and ERETNC instructions 
http://reviews.llvm.org/D10091


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239522 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-11 10:22:46 +00:00
Zoran Jovanovic
938cba6ae3 [mips][microMIPSr6] Change disassembler tests to one line format 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239519 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-06-11 09:42:10 +00:00
Zoran Jovanovic
dbab00a2d4 [mips][microMIPSr6] Implement SEB and SEH instructions 
Differential Revision: http://reviews.llvm.org/D9739


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238333 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-27 15:39:47 +00:00
Jozef Kolek
b8124ac882 [mips][microMIPSr6] Implement BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC and BNEZALC instructions 
This patch implements microMIPS32r6 BEQZALC, BGEZALC, BGTZALC, BLEZALC, BLTZALC
and BNEZALC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D10031


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238325 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-27 14:19:22 +00:00
Zoran Jovanovic
70d1005bbd [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructions 
Differential Revision: http://reviews.llvm.org/D8800


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237697 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-19 14:12:55 +00:00
Zoran Jovanovic
94ddfe5e09 [mips][microMIPSr6] Implement AND and ANDI instructions 
Differential Revision: http://reviews.llvm.org/D8772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237696 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-19 13:32:31 +00:00
Zoran Jovanovic
7004ac8b5a [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructions 
Differential Revision: http://reviews.llvm.org/D8769


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237685 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-19 11:21:37 +00:00
Jozef Kolek
1193b61df0 [mips][microMIPSr6] Implement LSA instruction 
This patch implements LSA instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8919


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237634 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-18 23:12:10 +00:00
Jozef Kolek
865eb964f3 [mips][microMIPSr6] Implement ALIGN and AUI instructions 
This patch implements ALIGN and AUI instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8782


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237563 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-18 11:44:30 +00:00
Jozef Kolek
cdecddaf1e [mips][microMIPSr6] Implement CLO and CLZ instructions 
This patch implements CLO and CLZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8553


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237257 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-13 14:18:11 +00:00
Jozef Kolek
043da74b89 [mips][microMIPSr6] Implement SELEQZ and SELNEZ instructions 
This patch implements SELEQZ and SELNEZ instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8497


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237158 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-12 17:39:32 +00:00
Jozef Kolek
5081399663 [mips][microMIPSr6] Implement ALUIPC and AUIPC instructions 
This patch implements ALUIPC and AUIPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8441


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236858 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-08 14:25:11 +00:00
Jozef Kolek
900e1d0766 [mips][microMIPSr6] Implement ADDIUPC and LWPC instructions 
This patch implements ADDIUPC and LWPC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8415


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236852 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-08 13:52:04 +00:00
Jozef Kolek
8359916759 [mips][microMIPSr6] Implement JIALC and JIC instructions 
This patch implements JIALC and JIC instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8389


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236748 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-07 17:12:23 +00:00
Daniel Sanders
898fd78e33 [mips][msa] Test basic operations for the N32 ABI too. 
Summary:
This required adding instruction aliases for dneg.

N64 will be enabled shortly but requires additional bugfixes.

Reviewers: vkalintiris

Reviewed By: vkalintiris

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9341


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236489 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-05-05 08:48:35 +00:00
Daniel Sanders
2e2b1db4d2 [mips] Sorted instructions in mips64r6 disassembly tests. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236223 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-30 10:52:42 +00:00
Zoran Jovanovic
6b6dc8a1f6 [mips][microMIPSr6] Implement MUL, MUH, MULU and MUHU instructions 
Differential Revision: http://reviews.llvm.org/D8894


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236131 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-29 17:23:22 +00:00
Zoran Jovanovic
3cf9e970d3 [mips][microMIPSr6] Implement SUB and SUBU instructions 
Differential Revision: http://reviews.llvm.org/D8764


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236118 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-29 16:22:46 +00:00
Zoran Jovanovic
b26cc705b0 [mips][microMIPSr6] Implement ADD, ADDU and ADDIU instructions 
Differential Revision: http://reviews.llvm.org/D8704


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236111 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-29 15:11:07 +00:00
Jozef Kolek
c589d1b3bc [mips][microMIPSr6] Implement CACHE and PREF instructions 
Implement CACHE and PREF instructions using mapping.

Differential Revision: http://reviews.llvm.org/D8893


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235379 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-21 11:17:25 +00:00
Jozef Kolek
382bee5224 [mips][microMIPSr6] Implement BITSWAP instruction 
Implement BITSWAP instruction using mapping.

Differential Revision: http://reviews.llvm.org/D8857


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235321 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-20 18:14:59 +00:00
Jozef Kolek
fc4915076f [mips][microMIPSr6] Implement disassembler support 
Implement disassembler support for microMIPS32r6.

Differential Revision: http://reviews.llvm.org/D8490


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235307 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-04-20 14:40:38 +00:00
Daniel Sanders
7eedd07d5e [mips] Add backend support for Mips32r[35] and Mips64r[35]. 
Summary:
These ISA's didn't add any instructions so they are almost identical to
Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA
revision in .MIPS.abiflags is 3 or 5 respectively instead of 2.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: tomatabacu, llvm-commits, atanasyan

Differential Revision: http://reviews.llvm.org/D7381


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229695 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-18 16:24:50 +00:00
Daniel Sanders
7b91359226 [mips] Merge disassemblers into a single implementation. 
Summary:
Currently we have Mips32 and Mips64 disassemblers and this causes the target
triple to affect the disassembly despite all the relevant information being in
the ELF header. These implementations do not need to be separate.

This patch merges them together such that the appropriate tables are checked
for the subtarget (e.g. Mips64 is checked when GP64 is enabled).

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7498

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228825 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-11 11:28:56 +00:00
Zoran Jovanovic
3c53772000 [mips][microMIPS] Implement movep instruction 
Differential Revision: http://reviews.llvm.org/D7465


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228703 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-10 16:36:20 +00:00
Jozef Kolek
c30c43de0f [mips][microMIPS] Add disassembler tests for 16-bit instructions BREAK16 and SDBBP16 
Differential Revision: http://reviews.llvm.org/D7443


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228687 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-10 13:20:51 +00:00
Jozef Kolek
cb5f9ea1ec [mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 and SWM16 
Differential Revision: http://reviews.llvm.org/D7436


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228683 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-10 12:41:13 +00:00
Vladimir Medic
d0fb85865a [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227430 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-29 11:33:41 +00:00
Jozef Kolek
a8c8e06c02 [mips][microMIPS] Implement LWGP instruction 
Differential Revision: http://reviews.llvm.org/D6650


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227325 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-28 17:27:26 +00:00
Vladimir Medic
c211591e17 When disassembler meets compact jump instructions for r6 it crashes as the access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227084 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-26 10:33:43 +00:00
Reid Kleckner
4fefe4cfb8 mips: Fix "XPASS" test results by removing 'not' commands 
These tests are asserting and crashing for me, and 'not' sees that as a
non-zero exit code instead of a signal code for obscure Windows reasons.
This causes the test to pass, giving me an unclean 'ninja check'.

The test is already XFAILd, so just run the test without 'not' and let
lit handle the failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226958 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-23 22:55:31 +00:00
Jozef Kolek
db8552c834 [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B 
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226657 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 12:39:30 +00:00
Jozef Kolek
16dbcd741f [mips][microMIPS] Implement ADDIUPC instruction 
Differential Revision: http://reviews.llvm.org/D6582


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226656 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 12:10:11 +00:00
Vladimir Medic
cde587f359 [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226652 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 10:47:36 +00:00
Jozef Kolek
8832c6b91e Reverted revision 226577. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226595 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-20 19:29:28 +00:00
Jozef Kolek
617b574ffb [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B 
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226577 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-20 16:45:27 +00:00
Daniel Sanders
d409aa7c4d [mips] 'CHECK :' is not a valid check directive. Fixed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226409 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-18 18:43:10 +00:00
Daniel Sanders
d752808096 [mips] Make whitespace in disassembler tests more consistent. NFC. 
The tests for the ISA's should now be approximately diffable. That is, the
output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines
for instructions that were added/removed to/from MIPS-I by MIPS-II. This
doesn't work perfectly at the moment due to ordering differences but it
should be close.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226408 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-18 18:38:36 +00:00
Daniel Sanders
56c484d0d3 [mips] Make whitespace of disassembler tests more consistent by removing blank lines. NFC. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226407 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-18 18:21:19 +00:00
Vladimir Medic
b6d562e480 Add disassembler tests for mips64r6 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226166 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-15 14:18:12 +00:00
Vladimir Medic
d83822e6d7 Add disassembler tests for mips32r6 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226165 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-15 14:11:38 +00:00
Vladimir Medic
e671c1cdb5 Add disassembler tests for mips64r2 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226164 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-15 14:06:34 +00:00
Vladimir Medic
dc67d7678a Add disassembler tests for mips64 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226151 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-15 08:50:20 +00:00
Vladimir Medic
81e68c9023 Add disassembler tests for mips32r2 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225980 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-14 11:35:22 +00:00
Vladimir Medic
8da9819ca7 Add disassembler tests for mips32r2 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225967 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-14 10:18:56 +00:00
Jozef Kolek
ad017096fc [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions 
Differential Revision: http://reviews.llvm.org/D5271


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225627 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-12 12:03:34 +00:00
Jozef Kolek
c623d0af3d [mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions 
Differential Revision: http://reviews.llvm.org/D5204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224785 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 19:55:34 +00:00
Jozef Kolek
e5fa612e9e [mips][microMIPS] Implement LWSP and SWSP instructions 
Differential Revision: http://reviews.llvm.org/D6416


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224771 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-23 16:16:33 +00:00
Zoran Jovanovic
78f6aad800 [mips][microMIPS] Implement SWP and LWP instructions 
Differential Revision: http://reviews.llvm.org/D5667


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224338 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 14:59:10 +00:00
Vladimir Medic
9e8621e99a Add disassembler tests for mips4 platform. There are no functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224335 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-16 13:02:25 +00:00