Commit Graph

166 Commits

Author SHA1 Message Date
ab1a0354ec Remove warning about 64-bit code on processor
that doesn't support it.  Per Chris.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47162 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-15 18:09:51 +00:00
be3bf42331 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
        subq    $8, %rsp
        leaq    _X(%rip), %rax
        movsd   8(%rax), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret
Now:
_main:
        subq    $8, %rsp
        movsd   _X+8(%rip), %xmm1
        movss   _X(%rip), %xmm0
        call    _t
        xorl    %ecx, %ecx
        movl    %ecx, %eax
        addq    $8, %rsp
        ret

Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl    %ecx, %ecx
movl    %ecx, %eax


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-07 08:53:49 +00:00
63ec90a6a8 SSE 4.1 Intrinsics and detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-03 07:18:54 +00:00
49964d6847 Enable PIC codegen on x86-64/linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46198 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-20 13:58:16 +00:00
e51775dc5e Use size_t to store Pos, avoid truncating value
on 64-bit builds.  Analysis and original patch
by Török Edwin.  Code audit found another place
with the same problem, also fixed here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45746 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-08 10:06:15 +00:00
7ad92d81e2 darwin9 and above support aligned common symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45494 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-02 19:44:55 +00:00
4ee451de36 Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 20:36:04 +00:00
fc05f402ea Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.

This should not change generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
2007-10-31 11:52:06 +00:00
f6844ca0e4 Mac OS X X86-64 low 4G address not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40701 91177308-0d34-0410-b5e6-96231b3b80d8
2007-08-01 23:45:51 +00:00
a99be51bf5 Here is the bulk of the sanitizing.
Almost all occurrences of "bytecode" in the sources have been eliminated.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
2007-07-05 17:07:56 +00:00
c398709525 In the event that some really old non-Intel or -AMD CPU is encountered...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36177 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 21:59:44 +00:00
22114c319a Before assuming that the original code didn't work for Athlon64, the person who
replaced it with a FIXME should have determined what did work.  Then he would have
realized that the code was in fact correct, and would have avoided breaking it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36173 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-16 21:48:58 +00:00
bb1ee05253 Add support for our first SSSE3 instruction "pmulhrsw".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
2007-04-10 22:10:25 +00:00
3b5ee73a13 Autodetect MMX & SSE stuff for AMD processors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35292 91177308-0d34-0410-b5e6-96231b3b80d8
2007-03-23 23:46:48 +00:00
5cbf985dcb For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
confusion with external linkage types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33663 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-30 20:08:39 +00:00
b10308e440 Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.

NOTEs: 1. Documentation will be updated soon.
       2. llvm-upgrade should be improved to translate csret => sret.
          Before this, there will be some unexpected test fails.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-28 13:31:35 +00:00
706535db86 Linux GOT indirect reference is only necessary in PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33441 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-22 21:34:25 +00:00
5032e5a613 * Fix one more bug in PIC codegen: extra load is needed for *all*
non-statics.
* Introduce new option to output zero-initialized data to .bss section.
This can reduce size of binaries. Enable it by default for ELF &
Cygwin/Mingw targets. Probably, Darwin should be also added.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33299 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-17 10:33:08 +00:00
7f70559bc4 * PIC codegen for X86/Linux has been implemented
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33136 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-12 19:20:47 +00:00
317848f4a1 Really big cleanup.
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32833 91177308-0d34-0410-b5e6-96231b3b80d8
2007-01-03 11:43:14 +00:00
2b2bc68884 Refactored JIT codegen for mingw32. Now we're using standart relocation
type for distinguish JIT & non-JIT instead of "dirty" hacks :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32745 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-22 22:29:05 +00:00
48c8e3de2f Fixed 80 cols & style violation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32720 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-20 20:40:30 +00:00
15fccf1d93 Fixed dllimported symbols support during JIT'ing. JIT on mingw32
platform should be more or less workable. At least, sim is running fine
under lli :)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32711 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-20 01:03:20 +00:00
f5da13367f What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-07 22:21:48 +00:00
7784ebc239 Factor out GVRequiresExtraLoad() from .h to .cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32048 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-30 22:42:55 +00:00
b4809b2b8f 16-byte stack alignment for X86-64 ELF. Patch by Dan Gohman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32004 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-29 02:00:40 +00:00
3b6f497873 Fix codegen for x86-64 on systems (like ppc or i386) that don't have 64-bit
features autodetected.  This fixes PR1010 and Regression/CodeGen/X86/xmm-r64.ll
on non-x86-64 hosts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31879 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-20 18:16:05 +00:00
aacf99964f Use movl+xchgl instead of pushl+popl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31572 91177308-0d34-0410-b5e6-96231b3b80d8
2006-11-08 20:35:37 +00:00
f896d1e247 Proper fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30993 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-17 00:24:49 +00:00
751c0e12db Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30985 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-16 21:00:37 +00:00
3cff9f8947 80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30770 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 18:57:51 +00:00
a26eb5e1a7 Still need to support -mcpu=<> or cross compilation will fail. Doh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30764 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 09:17:41 +00:00
abc346ceda Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30763 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 08:21:07 +00:00
88c1578011 It appears the inline asm in GetCpuIDAndInfo() may clobbers some registers if it isn't inlined (at < -O3). Force it to be inlined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30762 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-06 07:50:56 +00:00
8e0055de8a Formating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30722 91177308-0d34-0410-b5e6-96231b3b80d8
2006-10-04 18:33:00 +00:00
25ab690a43 Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-08 06:48:29 +00:00
cdb341dcfa Fix a cross-build issue. The asmsyntax shouldn't be affected by the build
host, it should be affected by the target.  Allow the command line option to
override in either case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30164 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-07 22:29:41 +00:00
05a059d5d8 Make the x86 asm flavor part of the subtarget info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30146 91177308-0d34-0410-b5e6-96231b3b80d8
2006-09-07 12:23:47 +00:00
54edc84000 Later models likely to have Yonah like attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28843 91177308-0d34-0410-b5e6-96231b3b80d8
2006-06-16 21:58:49 +00:00
932ad51fea X86 / Cygwin asm / alignment fixes.
Patch contributed by Anton Korobeynikov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28480 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-25 21:59:08 +00:00
7ccced634a x86 / Darwin PIC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-18 00:15:05 +00:00
18a8452f3d A bit more memset / memcpy optimization.
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-16 00:21:07 +00:00
ddf7532442 Duh
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26180 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 20:37:37 +00:00
968c178172 Remove -disable-x86-sse
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26179 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 20:30:14 +00:00
82eaf628b4 Enable SSE (for the right subtargets)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26169 91177308-0d34-0410-b5e6-96231b3b80d8
2006-02-14 08:07:58 +00:00
c4013d6772 Flesh out AMD family/models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25755 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 20:30:18 +00:00
216d281d0a Correctly determine CPU vendor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25754 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 19:48:34 +00:00
a349640b7f Use union instead of reinterpret_cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25751 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 18:47:32 +00:00
7617717496 Fix recognition of Intel CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25750 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 18:38:20 +00:00
c2fad16155 Is64Bit reflects the capability of the chip, not an aspect of the target os
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25749 91177308-0d34-0410-b5e6-96231b3b80d8
2006-01-28 18:23:48 +00:00