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23197 Commits

Author SHA1 Message Date
Anton Korobeynikov
0ae6124034 Add support for varargs functions for msp430. 
Patch by Job Noorman!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168440 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 17:28:27 +00:00
Anton Korobeynikov
6cbeb4d839 Add support for byval args. Patch by Job Noorman! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168439 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 17:23:03 +00:00
Rafael Espindola
6ee1e0867d Finish the renaming. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168437 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 16:56:33 +00:00
Jyotsna Verma
24d5025d8d Renamed HexagonImmediates.td -> HexagonOperands.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168434 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 16:28:18 +00:00
Craig Topper
9648782552 Fix execution domain for packed FMA4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168417 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 08:08:21 +00:00
Craig Topper
3dcefc864e Mark ISD::FMA as Legal instead of custom for x86 with FMA3/FMA4. Needed so that llvm.muladd can be converted to ISD::FMA for fp_contract. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168413 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 05:36:24 +00:00
Jakub Staszak
e845cedf4d Make calcLiveInMask method static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168409 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 00:59:34 +00:00
Jakub Staszak
6f05f21857 Make isScratchReg and isFPCopy methods static. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168407 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-21 00:50:57 +00:00
Jakub Staszak
8c67c03b0c Add obvious constantness. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168396 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-20 23:32:32 +00:00
Jyotsna Verma
7d1b42a842 Removing some unused instruction definitions from the Hexagon backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168388 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-20 22:14:23 +00:00
Elena Demikhovsky
4fe5405bdd Intel OCL built-ins calling conventions now support MacOS 32-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168359 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-20 09:37:57 +00:00
Eli Friedman
43147afd71 Mark FP_EXTEND form v2f32 to v2f64 as "expand" for ARM NEON. Patch by Pete Couperus. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168240 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-17 01:52:46 +00:00
Akira Hatanaka
94e472832f Initial implementation of MipsTargetLowering::isLegalAddressingMode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168230 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-17 00:25:41 +00:00
Weiming Zhao
8b149cbfc6 Rename methods like PairSRegs() to createSRegpairNode() to meet our coding 
style requirement.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168229 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-17 00:23:35 +00:00
Weiming Zhao
e56764bad1 Remove hard coded registers in ARM ldrexd and strexd instructions 
This patch replaces the hard coded GPR pair [R0, R1] of
Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with
even/odd GPRPair reg class.
Similar to the lowering of atomic_64 operation.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168207 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 21:55:34 +00:00
Anton Korobeynikov
b1a392e7c5 Make sure FABS on v2f32 and v4f32 is legal on ARM NEON 
This fixes PR14359


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168200 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 21:15:20 +00:00
Richard Osborne
ccc015d431 Fix handling of aliases to functions. 
An alias to a function should use pc relative addressing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168199 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 21:12:38 +00:00
Justin Holewinski
2085d00d09 [NVPTX] Order global variables in def-use order before emiting them in the final assembly 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168198 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 21:03:51 +00:00
Joe Abbey
48f63be368 Using const cast to alleviate a warning. 
A PR is being filed to address some code issues here.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168185 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 19:38:42 +00:00
Duncan Sands
dc7f174b5e Add the Erlang/HiPE calling convention, patch by Yiannis Tsiouris. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168166 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 12:36:39 +00:00
Craig Topper
d577552c66 Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of vector types. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168141 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 06:37:56 +00:00
Akira Hatanaka
a032dbd62f [mips] Fix delay slot filler so that instructions with register operand $1 are 
allowed in branch delay slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168131 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-16 02:39:34 +00:00
Eli Friedman
846ce8ea67 Mark FP_ROUND for converting NEON v2f64 to v2f32 as expand. Add a missing 
case to vector legalization so this actually works.

Patch by Pete Couperus.  Fixes PR12540.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168107 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 22:44:27 +00:00
Akira Hatanaka
0301bc54ad [mips] Add predicate HasFPIdx for floating-point indexed load instruction 
support and use it in place of HasMips32r2Or64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168089 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 21:17:13 +00:00
Adhemerval Zanella
e95ed2b7af PowerPC: Lowering floor intrinsic for Altivec 
This patch lowers the llvm.floor, llvm.ceil, llvm.trunc, and
llvm.nearbyint to Altivec instruction when using 4 single-precision
float vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 20:56:03 +00:00
Akira Hatanaka
c984657c74 Add assertions in MipsLongBranch which check the size of basic blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168078 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 20:05:11 +00:00
Jakub Staszak
1c1c49372c Return 0 instead of false. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168076 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 19:40:29 +00:00
Jakub Staszak
eaf77254d4 Simplify code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 19:05:23 +00:00
Dmitri Gribenko
79c07d2a36 Use empty parens for empty function parameter list instead of '(void)'. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 16:51:49 +00:00
Craig Topper
116bd168e1 Revert changing FNEG of v4f32 to Expand. It's legal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168030 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 08:09:46 +00:00
Craig Topper
b916904e68 Make FNEG and FABS of v4f32 Expand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168029 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 08:06:12 +00:00
Craig Topper
44e394cf61 Make a bunch of floating point operations on vectors Expand so that instruction selection won't fail. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168028 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 08:02:19 +00:00
Craig Topper
490104720d Add llvm.ceil, llvm.trunc, llvm.rint, llvm.nearbyint intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168025 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-15 06:51:10 +00:00
Jakub Staszak
3427f0aa7c Remove unneeded #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168006 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 23:58:57 +00:00
NAKAMURA Takumi
e8b0ae1fb6 NVPTXISelLowering.cpp: Fix warnings. [-Wunused-variable] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168001 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 23:46:15 +00:00
Eric Christopher
06b423452c Remove the CellSPU port. 
Approved by Chris Lattner.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167984 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 22:09:20 +00:00
Jakub Staszak
7454fc2e87 Fix invalid asserts, use llvm_unreachable instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167976 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 21:03:40 +00:00
Jyotsna Verma
cb02fa9d7f Added multiclass for post-increment load instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 20:38:48 +00:00
Benjamin Kramer
2dbe929685 X86: Enable SSE memory intrinsics even when stack alignment is less than 16 bytes. 
The stack realignment code was fixed to work when there is stack realignment and
a dynamic alloca is present so this shouldn't cause correctness issues anymore.

Note that this also enables generation of AVX instructions for memset
under the assumptions:
- Unaligned loads/stores are always fast on CPUs supporting AVX
- AVX is not slower than SSE
We may need some tweaked heuristics if one of those assumptions turns out not to
be true.

Effectively reverts r58317. Part of PR2962.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167967 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 20:08:40 +00:00
Nadav Rotem
50b66387e3 The code pattern "imm0_255_neg" is used for checking if an immediate value is a small negative number. 
This patch changes the definition of negative from -0..-255 to -1..-255. I am changing this because of
a bug that we had in some of the patterns that assumed that "subs" of zero does not set the carry flag.

rdar://12028498



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167963 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 19:39:15 +00:00
Justin Holewinski
a20067b5d4 [NVPTX] Implement custom lowering of loads/stores for i1 
Loads from i1 become loads from i8 followed by trunc
Stores to i1 become zext to i8 followed by store to i8

Fixes PR13291

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 19:19:16 +00:00
Jim Grosbach
3ca6382120 X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches. 
When an instruction as written requires 32-bit mode and we're assembling
in 64-bit mode, or vice-versa, issue a more specific diagnostic about
what's wrong.

rdar://12700702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 18:04:47 +00:00
Craig Topper
1ab489a42d Set FFLOOR of vectors to expand to keep intruction selection from failing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167922 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 08:11:25 +00:00
Craig Topper
55de339dad Factor out an overly replicated typecast. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167916 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 06:41:09 +00:00
Craig Topper
509bd72576 Set FFLOOR for vectors to expand on CellSPU to keep instruction selection from failing on llvm.floor of a vector. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167914 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 05:56:30 +00:00
Anton Korobeynikov
25efd6d556 Use TARGET2 relocation for TType references on ARM. 
Do some cleanup of the code while here.

Inspired by patch by Logan Chien!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167904 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-14 01:47:00 +00:00
Ulrich Weigand
ba6086818d Add (some) PowerPC TLS relocation types to ELF.h and 
generate them from PPCELFObjectWriter::getRelocTypeInner
as appropriate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167864 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-13 19:24:36 +00:00
Ulrich Weigand
8f887369cb Fix wrong PowerPC instruction opcodes for: 
- lwaux
 - lhzux
 - stbu


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167863 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-13 19:21:31 +00:00
Ulrich Weigand
4ff09818a9 Fix wrong PowerPC instruction encodings due to 
operand field name mismatches in:
 - AForm_3  (fmul, fmuls)
 - XFXForm_5 (mtcrf)
 - XFLForm (mtfsf)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167862 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-13 19:19:46 +00:00
Ulrich Weigand
18430436ca Fix instruction encoding for "bd(n)z" on PowerPC, 
by using a new instruction format BForm_1.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167861 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-13 19:15:52 +00:00