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Author SHA1 Message Date
Devang Patel
35fcd6557f Introduce DIBuilder. It is intended to be a front-end friendly interface to emit debuggging information entries in LLVM IR. 
To create debugging information for a pointer, using DIBUilder front-end just needs
	DBuilder.CreatePointerType(Ty, Size);
instead of
	DebugFactory.CreateDerivedType(llvm::dwarf::DW_TAG_pointer_type,
                                       TheCU, "", getOrCreateMainFile(),
                                       0, Size, 0, 0, 0, OCTy);



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118248 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 15:01:38 +00:00
Devang Patel
ab70ed41f3 Add getFile() to get DIFile of a DIType. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118247 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 14:56:34 +00:00
Duncan Sands
1e96bab329 In the calling convention logic, ValVT is always a legal type, 
and as such can be represented by an MVT - the more complicated
EVT is not needed.  Use MVT for ValVT everywhere.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 10:49:57 +00:00
Evan Cheng
416941d50f Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 05:19:35 +00:00
Chris Lattner
c07bd40a64 partition operand processing between aliases and instructions. 
Right now the code is partitioned but the behavior is the same.
This should be improved in the near future.   This removes some
uses of TheOperandList.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 02:11:18 +00:00
Chris Lattner
5f4280cd2d pull name slicing out of BuildInstructionOperandReference so 
it doesn't do any lexical stuff anymore.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118230 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 01:58:23 +00:00
Chris Lattner
ba3b5b6382 cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118228 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 01:55:23 +00:00
Chris Lattner
567820c1e0 replace SrcOpNum with SrcOpName, eliminating a numering dependency 
on the incoming operand list.  This also makes the code simpler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 01:42:59 +00:00
Daniel Dunbar
ea8e20696e System: Add llvm_execute_on_thread, which does what it says. 
- Primarily useful for running some code with a specified stack size, when
   pthreads are available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118222 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 01:26:25 +00:00
Jim Grosbach
70933266ae Add ARM fixup info for load/store label references. Probably will need a bit of 
tweaking when we start using it for object file emission or JIT, but it's a
start.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 01:12:30 +00:00
Bill Wendling
2f46f1f59c Add encoding for VSTR. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 00:59:42 +00:00
Chris Lattner
0bb780c0e0 strength reduce some code, resolving a fixme. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118219 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 00:57:06 +00:00
Chris Lattner
1d13bda737 take a big step to making aliases more general and less of a hack: 
now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118217 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 00:43:46 +00:00
Jakob Stoklund Olesen
8c42f48d02 Disable fancy splitting during spilling unless -extra-spiller-splits is given. 
This way, InlineSpiller does the same amount of splitting as the standard
spiller. Splitting should really be guided by the register allocator, and
doesn't belong in the spiller at all.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118216 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-04 00:32:32 +00:00
Jim Grosbach
806e80ef42 Teach ARM Target to use the tblgen support for generating an MC'ized 
CodeEmitter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118209 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 23:52:49 +00:00
Jim Grosbach
bd29a36043 Add rule to build MC'ized CodeEmitter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118207 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 23:46:01 +00:00
Jim Grosbach
60aaa76196 Support generating an MC'ized CodeEmitter directly. Maintain a reference to the 
Fixups list for the instruction so the operand encoders can add to it as
needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118206 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 23:38:14 +00:00
Owen Anderson
60f4870c22 Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization. 
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 23:15:26 +00:00
Owen Anderson
d966817f3c Add support for code generation of the one register with immediate form of vorr. 
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 22:44:51 +00:00
Jim Grosbach
35b2de012d trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118199 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 22:03:20 +00:00
Eric Christopher
d81f17acb4 Just return undef for invalid masks or elts, and since we're doing that, 
just do it earlier too.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 20:44:42 +00:00
Jakob Stoklund Olesen
964bc25e5a Let RegAllocBasic require MachineDominators - they are already available and 
splitting needs them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118194 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 20:39:26 +00:00
Jakob Stoklund Olesen
376dcbd6c2 Tag debug output as regalloc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 20:39:23 +00:00
Eric Christopher
e5b13cfdd0 Optimize generated code for integer materialization a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118192 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 20:21:17 +00:00
Chris Lattner
c0b14a250b rename Operand -> AsmOperand for clarity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118190 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 19:47:34 +00:00
Evan Cheng
949c910fb3 Fix test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118187 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:21:33 +00:00
Owen Anderson
7a25825033 Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead, 
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:16:27 +00:00
Dale Johannesen
d5ce456161 This test assumes SSE is present; that is not the default 
on non-X86 hosts.  Hopefully fixes ppc-host buildbot.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 18:08:41 +00:00
Bob Wilson
d168cef664 Add codegen patterns for VST1-lane instructions. Radar 8599955. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118176 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:24:53 +00:00
Bob Wilson
3468c2ee20 Check for extractelement with a variable operand for the element number. 
For NEON we had been assuming this was always an immediate constant.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:24:50 +00:00
Mikhail Glushenkov
d66f2b74f2 Rename FindExecutable to PrependMainExecutablePath. 
Makes it more clear that it is just a path manipulation function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118174 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:14:16 +00:00
Mikhail Glushenkov
544fba1362 80-col violations, trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118173 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 16:14:07 +00:00
Duncan Sands
391f5bce04 Rename PointsToLocalMemory to PointsToLocalOrConstantMemory to make 
the code more self-documenting.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118171 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 14:45:05 +00:00
Duncan Sands
cdfad36b40 Simplify uses of MVT and EVT. An MVT can be compared directly 
with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 12:17:33 +00:00
Duncan Sands
538b0cdc76 Fix a comment typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118168 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 11:55:03 +00:00
Duncan Sands
1440e8b918 Inside the calling convention logic LocVT is always a simple 
value type, so there is no point in passing it around using
an EVT.  Use the simpler MVT everywhere.  Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 11:35:31 +00:00
Eric Christopher
caebdd44f3 If we have an undef mask our Elt will be -1 for our access, handle 
this by using an undef as a pointer.

Fixes rdar://8625016


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118164 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 09:36:40 +00:00
Duncan Sands
e3f75a3979 Fix typo, pointed out by Trevor Harmon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118163 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 08:16:50 +00:00
Evan Cheng
dfed19fe2c Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 06:34:55 +00:00
Evan Cheng
bc7deb0f75 Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 05:14:24 +00:00
Bill Wendling
cdbbec43a8 Put the PC encoding in the correct bit position. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118151 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 04:57:44 +00:00
Eric Christopher
000cf708ef Invert these branches by default, it makes assembly comparisons a little 
easier to read.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118148 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 04:29:11 +00:00
Bill Wendling
92b5a2eb16 The MC code couldn't handle ARM LDR instructions with negative offsets: 
vldr.64 d1, [r0, #-32]

The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:49:29 +00:00
Dan Gohman
394d6298bc Fix DAGCombiner to avoid going into an infinite loop when it 
encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118143 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:47:46 +00:00
Jim Grosbach
2915eb4430 Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:35:15 +00:00
Jim Grosbach
0a2287b909 Remove the no longer used 'Modifier' optional operand to the ARM 
printOperand() asm printer helper functions. rdar://8425198

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:11:15 +00:00
Jim Grosbach
496e2b2908 Remove unused function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:07:48 +00:00
Jim Grosbach
e6913600c7 Break ARM addrmode4 (load/store multiple base address) into its constituent 
parts. Represent the operation mode as an optional operand instead.
rdar://8614429

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 01:01:43 +00:00
Evan Cheng
8239daf7c8 Two sets of changes. Sorry they are intermingled. 
1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
   "optimize for latency". Call instructions don't have the right latency and
   this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
   not # of micro-ops since multi-latency instructions is completely executed
   even when the predicate is false. Also, some instruction will be "slower"
   when they are predicated due to the register def becoming implicit input.
   rdar://8598427


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118135 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 00:45:17 +00:00
Evan Cheng
41957f6eb2 Modify scheduling itineraries to correct instruction latencies (not operand 
latencies) of loads.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118134 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-11-03 00:40:22 +00:00