Craig Topper
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5679ec3b52
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Add X86 SARX, SHRX, and SHLX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142779 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-10-23 22:18:24 +00:00 |
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Craig Topper
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75485d6746
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Add X86 RORX instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142741 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-10-23 07:34:00 +00:00 |
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Craig Topper
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717cdb0df8
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Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142480 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-10-19 07:48:35 +00:00 |
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Craig Topper
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ee62e4f6d1
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Add X86 PEXTR and PDEP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142141 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-10-16 16:50:08 +00:00 |
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Craig Topper
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b53fa8bf19
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Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-10-16 07:55:05 +00:00 |
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Craig Topper
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17730847d5
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Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-10-16 03:51:13 +00:00 |
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Craig Topper
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566f233ba6
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Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
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2011-10-15 20:46:47 +00:00 |
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