Commit Graph

17 Commits

Author SHA1 Message Date
David Goodwin
87d21b92fc Allow target to specify regclass for which antideps will only be broken along the critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-13 19:52:48 +00:00
David Goodwin
c2e8a7e8d2 Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 00:48:55 +00:00
David Goodwin
0855dee564 Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-10 00:15:47 +00:00
David Goodwin
4c3715c2e5 Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-22 23:19:17 +00:00
Evan Cheng
fa16354e03 Change createPostRAScheduler so it can be turned off at llc -O1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-16 21:06:15 +00:00
David Goodwin
0dad89fa94 Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-30 00:10:16 +00:00
David Goodwin
dc4bdcdef1 Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19 16:08:58 +00:00
David Goodwin
710461688b Add callback to allow target to adjust latency of schedule dependency edge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78910 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 16:05:04 +00:00
Dan Gohman
8749b61178 Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction
variables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-16 03:35:01 +00:00
Dan Gohman
707e018423 Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal
on any current target and aren't optimized in DAGCombiner. Instead
of using intermediate nodes, expand the operations, choosing between
simple loads/stores, target-specific code, and library calls,
immediately.

Previously, the code to emit optimized code for these operations
was only used at initial SelectionDAG construction time; now it is
used at all times. This fixes some cases where rep;movs was being
used for small copies where simple loads/stores would be better.

This also cleans up code that checks for alignments less than 4;
let the targets make that decision instead of doing it in
target-independent code. This allows x86 to use rep;movs in
low-alignment cases.

Also, this fixes a bug that resulted in the use of rep;stos for
memsets of 0 with non-constant memory size when the alignment was
at least 4. It's better to use the library in this case, which
can be significantly faster when the size is large.

This also preserves more SourceValue information when memory
intrinsics are lowered into simple loads/stores.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-12 04:36:06 +00:00
Chris Lattner
7ed47a1335 Don't attribute in file headers anymore. See llvmdev for the
discussion of this change.  Boy are my fingers tired. ;-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45411 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-29 19:59:42 +00:00
Rafael Espindola
f1ba1cad38 Move the LowerMEMCPY and LowerMEMCPYCall to a common place.
Thanks for the suggestions Bill :-)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43742 91177308-0d34-0410-b5e6-96231b3b80d8
2007-11-05 23:12:20 +00:00
Jim Laskey
3b1cf89edc Remove unneeded include.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32489 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12 19:36:53 +00:00
Jim Laskey
9a7dfa3fd4 Rollback changes to take a different tack.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32488 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12 19:26:50 +00:00
Jim Laskey
55a7ec33d7 Honor the command line specification for machine type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32483 91177308-0d34-0410-b5e6-96231b3b80d8
2006-12-12 16:07:33 +00:00
Nate Begeman
0e219eb9b8 Clean up the TargetSubtarget class a bit, removing an unnecessary argument
to the constructor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22392 91177308-0d34-0410-b5e6-96231b3b80d8
2005-07-12 02:41:19 +00:00
Nate Begeman
fb5792f416 Implement Subtarget support
Implement the X86 Subtarget.

This consolidates the checks for target triple, and setting options based
on target triple into one place.  This allows us to convert the asm printer
and isel over from being littered with "forDarwin", "forCygwin", etc. into
just having the appropriate flags for each subtarget feature controlling
the code for that feature.

This patch also implements indirect external and weak references in the
X86 pattern isel, for darwin.  Next up is to convert over the asm printers
to use this new interface.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22389 91177308-0d34-0410-b5e6-96231b3b80d8
2005-07-12 01:41:54 +00:00