Commit Graph

62 Commits

Author SHA1 Message Date
Dan Gohman
a8dab36f3d Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;
if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 22:42:31 +00:00
Dan Gohman
84023e0fbe Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn().
 - Eschew ST0 and ST1 for return values.
 - Fix the PIC base register initialization so that it doesn't ever
   fail to end up the top of the entry block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-10 09:00:22 +00:00
Bob Wilson
02266e29f9 --- Reverse-merging r107947 into '.':
U    utils/TableGen/FastISelEmitter.cpp
--- Reverse-merging r107943 into '.':
U    test/CodeGen/X86/fast-isel.ll
U    test/CodeGen/X86/fast-isel-loads.ll
U    include/llvm/Target/TargetLowering.h
U    include/llvm/Support/PassNameParser.h
U    include/llvm/CodeGen/FunctionLoweringInfo.h
U    include/llvm/CodeGen/CallingConvLower.h
U    include/llvm/CodeGen/FastISel.h
U    include/llvm/CodeGen/SelectionDAGISel.h
U    lib/CodeGen/LLVMTargetMachine.cpp
U    lib/CodeGen/CallingConvLower.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
U    lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
U    lib/CodeGen/SelectionDAG/FastISel.cpp
U    lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
U    lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
U    lib/CodeGen/SelectionDAG/InstrEmitter.cpp
U    lib/CodeGen/SelectionDAG/TargetLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.cpp
U    lib/Target/XCore/XCoreISelLowering.h
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86FastISel.cpp
U    lib/Target/X86/X86ISelLowering.h


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 16:37:18 +00:00
Dan Gohman
bf87e24917 Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emitting
a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107943 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-09 00:39:23 +00:00
Jim Grosbach
d27946d1d4 grammar tweak in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-30 21:27:56 +00:00
Rafael Espindola
d31f972bd3 Add a VT argument to getMinimalPhysRegClass and replace the copy related uses
of getPhysicalRegisterRegClass with it.

If we want to make a copy (or estimate its cost), it is better to use the
smallest class as more efficient operations might be possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107140 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 14:02:34 +00:00
Duncan Sands
b447c4e65b Remove variables which are assigned to but for which the value
is not used.  Spotted by gcc-4.6.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-25 14:48:39 +00:00
Bill Wendling
10707f3b44 It's possible that a flag is added to the SDNode that points back to the
original SDNode. This is badness. Also, this function allows one SDNode to point
multiple flags to another SDNode. Badness as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106793 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-24 22:00:37 +00:00
Bill Wendling
151d26d15d MorphNodeTo doesn't preserve the memory operands. Because we're morphing a node
into the same node, but with different non-memory operands, we need to replace
the memory operands after it's finished morphing.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106643 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 18:16:24 +00:00
Dan Gohman
403a8cdda5 Use A.append(...) instead of A.insert(A.end(), ...) when A is a
SmallVector, and other SmallVector simplifications.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-21 19:47:52 +00:00
Evan Cheng
302ef834e0 Code refactoring, no functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105775 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-10 02:09:31 +00:00
Evan Cheng
046fa3f90a Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:26:21 +00:00
Evan Cheng
1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 23:26:43 +00:00
Evan Cheng
15a16def6e Add a hybrid bottom up scheduler that reduce register usage while avoiding
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 06:13:19 +00:00
Evan Cheng
e163168aab Code clean up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104173 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 22:42:23 +00:00
Dan Gohman
af1d8ca44a Get rid of the EdgeMapping map. Instead, just check for BasicBlock
changes before doing phi lowering for switches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102809 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:01:06 +00:00
Dan Gohman
891ff8fbd6 EmitDbgValue doesn't need its EdgeMapping argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102742 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-30 19:35:33 +00:00
Dale Johannesen
fdb42fa5fe Add DBG_VALUE handling for byval parameters; this
produces a comment on targets that support it, but
the Dwarf writer is not hooked up yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 20:06:49 +00:00
Evan Cheng
962021bc7f - Move TargetLowering::EmitTargetCodeForFrameDebugValue to TargetInstrInfo and rename it to emitFrameIndexDebugValue.
- Teach spiller to modify DBG_VALUE instructions to reference spill slots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102323 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-26 07:38:55 +00:00
Dan Gohman
3fb150a902 Fix -Wcast-qual warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101655 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-17 17:42:52 +00:00
Evan Cheng
4ec9bd9a6f Scheduler assumes SDDbgValue nodes are in source order. That's true currently. But add an assertion to verify it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99501 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 07:16:57 +00:00
Evan Cheng
167bda4baa Remove a fixme that doesn't make sense any more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99489 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 06:02:53 +00:00
Evan Cheng
bfcb305189 Change how dbg_value sdnodes are converted into machine instructions. Their placement should be determined by the relative order of incoming llvm instructions. The scheduler will now use the SDNode ordering information to determine where to insert them. A dbg_value instruction is inserted after the instruction with the last highest source order and before the instruction with the next highest source order. It will optimize the placement by inserting right after the instruction that produces the value if they have consecutive order numbers.
Here is a theoretical example that illustrates why the placement is important.

tmp1 = 
store tmp1 -> x
...
tmp2 = add ...
...
call
...
store tmp2 -> x

Now mem2reg comes along:

tmp1 = 
dbg_value (tmp1 -> x)
...
tmp2 = add ...
...
call
...
dbg_value (tmp2 -> x)

When the debugger examine the value of x after the add instruction but before the call, it should have the value of tmp1.

Furthermore, for dbg_value's that reference constants, they should not be emitted at the beginning of the block (since they do not have "producers").

This patch also cleans up how SDISel manages DbgValue nodes. It allow a SDNode to be referenced by multiple SDDbgValue nodes. When a SDNode is deleted, it uses the information to find the SDDbgValues and invalidate them. They are not deleted until the corresponding SelectionDAG is destroyed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99469 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-25 01:38:16 +00:00
Evan Cheng
a8efe28a44 Rename SDDbgValue.h to SDNodeDbgValue.h for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98513 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-14 19:56:39 +00:00
Dale Johannesen
bfdf7f3852 Progress towards shepherding debug info through SelectionDAG.
No functional effect yet.  This is still evolving and should
not be viewed as final.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-10 22:13:47 +00:00
Chris Lattner
736a6ea3a2 Change the scheduler from adding nodes in allnodes order
to adding them in a determinstic order (bottom up from 
the root) based on the structure of the graph itself.

This updates tests for some random changes, interesting
bits: CodeGen/Blackfin/promote-logic.ll no longer crashes.
I have no idea why, but that's good right?

CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but
now compiles to have one fewer constant pool entry, making
the expected load that was being folded disappear.  Since it
is an unreduced mass of gnast, I just removed it.

This fixes PR6370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97023 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-24 06:11:37 +00:00
Evan Cheng
42dae2d5ba Enable pre-regalloc scheduling load clustering by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94255 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 23:49:45 +00:00
Evan Cheng
c589e03865 Teach pre-regalloc scheduler to schedule loads from nearby addresses. It may improve cache locality. This is controlled by -cluster-loads for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94148 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-22 03:36:51 +00:00
David Greene
84fa8229bb Change errs() to dbgs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92581 91177308-0d34-0410-b5e6-96231b3b80d8
2010-01-05 01:25:11 +00:00
Bill Wendling
b4e6a5df5d Changes from review:
- Move DisableScheduling flag into TargetOption.h
- Move SDNodeOrdering into its own header file. Give it a minimal interface that
  doesn't conflate construction with storage.
- Move assigning the ordering into the SelectionDAGBuilder.

This isn't used yet, so there should be no functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91727 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-18 23:32:53 +00:00
Daniel Dunbar
819309efec Reapply r91392, it was only unmasking the bug, and since TOT is still broken having it reverted does no good.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91560 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 20:10:05 +00:00
Daniel Dunbar
222518d0bb Revert "Initial work on disabling the scheduler. This is a work in progress, and
this", this broke llvm-gcc bootstrap for release builds on
x86_64-apple-darwin10.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91533 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-16 10:56:02 +00:00
Bill Wendling
614407a9d2 Initial work on disabling the scheduler. This is a work in progress, and this
stuff isn't used just yet.

We want to model the GCC `-fno-schedule-insns' and `-fno-schedule-insns2'
flags. The hypothesis is that the people who use these flags know what they are
doing, and have hand-optimized the C code to reduce latencies and other
conflicts.

The idea behind our scheme to turn off scheduling is to create a map "on the
side" during DAG generation. It will order the nodes by how they appeared in the
code. This map is then used during scheduling to get the ordering.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91392 91177308-0d34-0410-b5e6-96231b3b80d8
2009-12-15 01:54:51 +00:00
Dan Gohman
bcea859fc1 Create a new InstrEmitter class for translating SelectionDAG nodes
into MachineInstrs. This is mostly just moving the code from
ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr
emitting from scheduling.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83699 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-10 01:32:21 +00:00
Dan Gohman
98976e4dcd The ScheduleDAG framework now requires an AliasAnalysis argument, though
it isn't needed in the ScheduleDAGSDNodes schedulers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83691 91177308-0d34-0410-b5e6-96231b3b80d8
2009-10-09 23:33:48 +00:00
Dan Gohman
c76909abfe Improve MachineMemOperand handling.
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-25 20:36:54 +00:00
Duncan Sands
c2d98bc0d6 Remove some not-really-used variables, as warned
about by icc (#593, partial).  Patch by Erick Tryzelaar.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81115 91177308-0d34-0410-b5e6-96231b3b80d8
2009-09-06 12:41:19 +00:00
David Goodwin
dc4bdcdef1 Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79425 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-19 16:08:58 +00:00
David Goodwin
710461688b Add callback to allow target to adjust latency of schedule dependency edge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78910 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-13 16:05:04 +00:00
Owen Anderson
825b72b057 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-11 20:47:22 +00:00
Owen Anderson
e50ed30282 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-10 22:56:29 +00:00
Daniel Dunbar
1cd1d98232 Move more to raw_ostream, provide support for writing MachineBasicBlock,
LiveInterval, etc to raw_ostream.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76965 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-24 10:36:58 +00:00
Dale Johannesen
874ae251c3 Revert 72707 and 72709, for the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72712 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-02 03:12:52 +00:00
Dale Johannesen
4150d83abe Make the implicit inputs and outputs of target-independent
ADDC/ADDE use MVT::i1 (later, whatever it gets legalized to)
instead of MVT::Flag.  Remove CARRY_FALSE in favor of 0; adjust
all target-independent code to use this format.

Most targets will still produce a Flag-setting target-dependent
version when selection is done.  X86 is converted to use i32
instead, which means TableGen needs to produce different code
in xxxGenDAGISel.inc.  This keys off the new supportsHasI1 bit
in xxxInstrInfo, currently set only for X86; in principle this
is temporary and should go away when all other targets have
been converted.  All relevant X86 instruction patterns are
modified to represent setting and using EFLAGS explicitly.  The
same can be done on other targets.

The immediate behavior change is that an ADC/ADD pair are no
longer tightly coupled in the X86 scheduler; they can be
separated by instructions that don't clobber the flags (MOV).
I will soon add some peephole optimizations based on using
other instructions that set the flags to feed into ADC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72707 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-01 23:27:20 +00:00
Dan Gohman
8cccf0ef0c Don't set SUnit::hasPhysRegDefs to true unless the defs are
actually have uses, which reflects the way it's used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67540 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 17:39:36 +00:00
Dan Gohman
3974667c1a Add a new bit to SUnit to record whether a node has implicit physreg
defs, regardless of whether they are actually used.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67528 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-23 16:10:52 +00:00
Dan Gohman
db95fa131a Simplify this code; use a while instead of an if and a do-while.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67400 91177308-0d34-0410-b5e6-96231b3b80d8
2009-03-20 20:42:23 +00:00
Dan Gohman
47ac0f0c7c When scheduling a block in parts, keep track of the overall
instruction index across each part. Instruction indices are used
to make live range queries, and live ranges can extend beyond
scheduling region boundaries.

Refactor the ScheduleDAGSDNodes class some more so that it
doesn't have to worry about this additional information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64288 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-11 04:27:20 +00:00
Dan Gohman
84fbac5809 Move ScheduleDAGSDNodes.h to be a private header. Front-ends
that previously included this header should include
SchedulerRegistry.h instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63937 91177308-0d34-0410-b5e6-96231b3b80d8
2009-02-06 17:22:58 +00:00
Evan Cheng
e57187cbe3 CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62356 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-16 20:57:18 +00:00