Commit Graph

91125 Commits

Author SHA1 Message Date
Evan Cheng
3a6b7d38a7 __sincosf_stret returns sinf / cosf in bits 0:31 and 32:63 of xmm0, not in
xmm0 / xmm1.

rdar://13599493


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 01:26:07 +00:00
Andrew Trick
5ed028385c Generalize the PassConfig API and remove addFinalizeRegAlloc().
The target hooks are getting out of hand. What does it mean to run
before or after regalloc anyway? Allowing either Pass* or AnalysisID
pass identification should make it much easier for targets to use the
substitutePass and insertPass APIs, and create less need for badly
named target hooks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179140 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-10 01:06:56 +00:00
Jack Carter
a9a5c537ad Mips specific inline asm operand modifier 'D'
Modifier 'D' is to use the second word of a double integer.

We had previously implemented the pure register varient of 
the modifier and this patch implements the memory reference.



#include "stdio.h"

int b[8] = {0,1,2,3,4,5,6,7};
void main()
{
    int i;
    
    // The first word. Notice, no 'D'
    {asm (
    "lw    %0,%1;"
    : "=r" (i)
    : "m" (*(b+4))
    );}
    
    printf("%d\n",i);

    // The second word
    {asm (
    "lw    %0,%D1;"
    : "=r" (i)
    : "m" (*(b+4))
    );}
    
    printf("%d\n",i);
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 23:19:50 +00:00
Hal Finkel
7eb0d8148e Allow PPC B and BLR to be if-converted into some predicated forms
This enables us to form predicated branches (which are the same conditional
branches we had before) and also a larger set of predicated returns (including
instructions like bdnzlr which is a conditional return and loop-counter
decrement all in one).

At the moment, if conversion does not capture all possible opportunities. A
simple example is provided in early-ret2.ll, where if conversion forms one
predicated return, and then the PPCEarlyReturn pass picks up the other one. So,
at least for now, we'll keep both mechanisms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 22:58:37 +00:00
Bob Wilson
58ddf52892 Fix some comment typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179132 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 22:15:51 +00:00
Chad Rosier
df1087061c Cleanup. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 20:58:48 +00:00
Chad Rosier
bad493e912 Cleanup. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 20:44:09 +00:00
Rafael Espindola
27554ee1d8 Remove unused method and default values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 20:35:08 +00:00
Eric Christopher
af12ad7c92 Update the version of dwarf we say we're emitting to at least 3.
Deals with a dwarf2 -> dwarf3 DW_FORM_ref_addr change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179122 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 20:22:47 +00:00
Chad Rosier
3eb6d7fcd0 Revert r179115 as it looks to have killed the ASan tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:59:12 +00:00
Chandler Carruth
239e1e4938 Rationalize the formatting of these case labels. Having two sorted
columns is essentially impossible to edit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:46:46 +00:00
Reed Kotler
a430cb613b This patch enables llvm to switch between compiling for mips32/mips64
and mips16 on a per function basis.

Because this patch is somewhat involved I have provide an overview of the
key pieces of it.

The patch is written so as to not change the behavior of the non mixed
mode. We have tested this a lot but it is something new to switch subtargets
so we don't want any chance of regression in the mainline compiler until
we have more confidence in this.

Mips32/64 are very different from Mip16 as is the case of ARM vs Thumb1.
For that reason there are derived versions of the register info, frame info, 
instruction info and instruction selection classes.

Now we register three separate passes for instruction selection.
One which is used to switch subtargets (MipsModuleISelDAGToDAG.cpp) and then
one for each of the current subtargets (Mips16ISelDAGToDAG.cpp and
MipsSEISelDAGToDAG.cpp).

When the ModuleISel pass runs, it determines if there is a need to switch
subtargets and if so, the owning pointers in MipsTargetMachine are
appropriately changed.

When 16Isel or SEIsel is run, they will return immediately without doing
any work if the current subtarget mode does not apply to them.

In addition, MipsAsmPrinter needs to be reset on a function basis.

The pass BasicTargetTransformInfo is substituted with a null pass since the
pass is immutable and really needs to be a function pass for it to be
used with changing subtargets. This will be fixed in a follow on patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:46:01 +00:00
Nadav Rotem
8383b539ff Add support for bottom-up SLP vectorization infrastructure.
This commit adds the infrastructure for performing bottom-up SLP vectorization (and other optimizations) on parallel computations.
The infrastructure has three potential users:

  1. The loop vectorizer needs to be able to vectorize AOS data structures such as (sum += A[i] + A[i+1]).

  2. The BB-vectorizer needs this infrastructure for bottom-up SLP vectorization, because bottom-up vectorization is faster to compute.

  3. A loop-roller needs to be able to analyze consecutive chains and roll them into a loop, in order to reduce code size. A loop roller does not need to create vector instructions, and this infrastructure separates the chain analysis from the vectorization.

This patch also includes a simple (100 LOC) bottom up SLP vectorizer that uses the infrastructure, and can vectorize this code:

void SAXPY(int *x, int *y, int a, int i) {
  x[i]   = a * x[i]   + y[i];
  x[i+1] = a * x[i+1] + y[i+1];
  x[i+2] = a * x[i+2] + y[i+2];
  x[i+3] = a * x[i+3] + y[i+3];
}



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179117 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:44:35 +00:00
Eric Christopher
376e05fd7b Make check depend on all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:42:12 +00:00
Chad Rosier
d4727e3798 [ms-inline asm] Use parsePrimaryExpr in lieu of parseExpression if we need to
parse an identifier.  Otherwise, parseExpression may parse multiple tokens,
which makes it impossible to properly compute an immediate displacement.
An example of such a case is the source operand (i.e., [Symbol + ImmDisp]) in
the below example:

 __asm mov eax, [Symbol + ImmDisp]

The existing test cases exercise this patch.
rdar://13611297


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179115 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:34:59 +00:00
Eric Christopher
e0828ec602 The .dwo section shouldn't contain the unrelocated values (and
therefore not at all) of the pc or statement list. We also don't
need to emit the compilation dir so save so space and time
and don't bother.

Fix up the testcase accordingly and verify that we don't emit
the attributes or the items that they use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179114 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 19:23:15 +00:00
Hal Finkel
13049aef8a Cleanup PPCEarlyReturn
Some general cleanup and only scan the end of a BB for branches (once we're
done with the terminators and debug values, then there should not be any other
branches). These address post-commit review suggestions by Bill Schmidt.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179112 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 18:25:18 +00:00
Nadav Rotem
8e4df489d0 Revert r176408 and r176407 to address PR15540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 18:16:05 +00:00
Chad Rosier
b976e407dc [ms-inline asm] Maintain a StringRef to reference a symbol in a parsed operand,
rather than deriving the StringRef from the Start and End SMLocs.

Using the Start and End SMLocs works fine for operands such as [Symbol], but
not for operands such as [Symbol + ImmDisp].  All existing test cases that
reference a variable exercise this patch.
rdar://13602265



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179109 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 17:53:49 +00:00
Benjamin Kramer
6fac1fbf30 DAGCombiner: Fold a shuffle on CONCAT_VECTORS into a new CONCAT_VECTORS if possible.
This pattern occurs in SROA output due to the way vector arguments are lowered
on ARM.

The testcase from PR15525 now compiles into this, which is better than the code
we got with the old scalarrepl:
_Store:
	ldr.w	r9, [sp]
	vmov	d17, r3, r9
	vmov	d16, r1, r2
	vst1.8	{d16, d17}, [r0]
	bx	lr

Differential Revision: http://llvm-reviews.chandlerc.com/D647

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179106 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 17:41:43 +00:00
Hal Finkel
f6f8198d85 Use virtual base registers on PPC
On PowerPC, non-vector loads and stores have r+i forms; however, in functions
with large stack frames these were not being used to access slots far from the
stack pointer because such slots were out of range for the signed 16-bit
immediate offset field. This increases register pressure because we need a
separate register for each offset (when the r+r form is used). By enabling
virtual base registers, we can deal with large stack frames without unduly
increasing register pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 17:27:09 +00:00
Hal Finkel
307b8535ee Convert test PowerPC/2007-09-07-LoadStoreIdxForms to FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179104 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 17:26:55 +00:00
Eli Bendersky
d7170ea5a8 Rewrite test/Linker tests to use FileCheck instead of grep.
Some translations here are not 1x1 because there are grep|grep
chains that are non-trivial to implement in terms of FileCheck features. I
made an effort for the tests to remain as similar as possible; do let me know
if you notice anything fishy. The good news are that some buggy tests were
fixed (grep | not grep - a bug waiting to happen).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 16:51:13 +00:00
Rafael Espindola
f6cfc15705 Convert MachOObjectFile to a template.
For now it is templated only on being 64 or 32 bits. I will add little/big
endian next.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179097 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 14:49:08 +00:00
Alexey Samsonov
32a3e78304 DWARF parser: Fix DWARF-2/3 incompatibility: size of DW_FORM_ref_addr is the same as DW_FORM_addr in DWARF2, and is 4/8 bytes on 32/64-bit DWARF starting from DWARF3. Adding a test for this is a huge pain - generating and uploading pre-built binary with DWARF3 debug info is way too ugly, and writing fine-grained unittests for DebugInfo is impossible, as it doesn't expose any headers in include/llvm. That said, I'm going to choose the second approach and submit the patch exposing DebugInfo headers for review soon enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179095 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 14:09:42 +00:00
Michael Gottesman
3c5aaa20ee Converted 8x tests of SimplifyCFG to use FileCheck instead of grep.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179087 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 05:18:53 +00:00
Jakob Stoklund Olesen
1b133a478b Extract a function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179086 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 05:11:52 +00:00
Nadav Rotem
fa335e4060 Remove the confusing sentence.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 04:48:40 +00:00
Nadav Rotem
e43e2d8cf0 Revert 179071 because it is not the right way to support non standard new/new[] operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179084 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 04:43:46 +00:00
Jakob Stoklund Olesen
6ed9284c2b Compute correct frame sizes for SPARC v9 64-bit frames.
The save area is twice as big and there is no struct return slot. The
stack pointer is always 16-byte aligned (after adding the bias).

Also eliminate the stack adjustment instructions around calls when the
function has a reserved stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 04:37:47 +00:00
Rafael Espindola
8faf7df144 More uses for SymbolTableEntryBase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179076 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 01:04:06 +00:00
Rafael Espindola
7df9c57651 Add a SymbolTableEntryBase.
Use it when we don't need to know if we have a 32 or 64 bit SymbolTableEntry.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 00:22:58 +00:00
Joe Groff
b3d25a940c Fix PointerIntPair to be enum class compatible.
Some parts of PointerIntPair assumed that the IntType of the pair was implicitly
convertible to intptr_t, which is not the case for enum class values. Add a
static_cast<intptr_t> to make these conversions explicit and allow
PointerIntPair to be used with an enum class IntType. While we're here, rename
some of the argument values so we don't have variables named "Int" floating
around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179073 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-09 00:01:51 +00:00
Rafael Espindola
3388589fc1 Add a SectionBase struct.
Use it to share code and when we don't need to know if we have a 32 or 64
bit Section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 23:57:13 +00:00
Nadav Rotem
0a9b452aa4 c++ new operators are not malloc-like functions because they do not return uninitialized memory.
Users may overide new-operators and implement any function that they like.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 23:40:47 +00:00
NAKAMURA Takumi
92c3742319 InstructionSimplify.cpp: Fix a ligature, "fi", to get rid of utf8 in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179066 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 23:05:21 +00:00
Shuxin Yang
4fd00c55d0 Redo the fix Benjamin Kramer committed in r178793 about iterator invalidation in Reassociate.
I brazenly think this change is slightly simpler than r178793 because: 
  - no "state" in functor
  - "OpndPtrs[i]" looks simpler than "&Opnds[OpndIndices[i]]" 

  While I can reproduce the probelm in Valgrind, it is rather difficult to come up
a standalone testing case. The reason is that when an iterator is invalidated,
the stale invalidated elements are not yet clobbered by nonsense data, so the
optimizer can still proceed successfully. 

  Thank Benjamin for fixing this bug and generously providing the test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179062 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 22:00:43 +00:00
Nadav Rotem
df4381b578 Update the docs about the fact that the loop vectorizer is enabled by default for -O3.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 21:34:49 +00:00
Rafael Espindola
335f1d46d8 Template the MachO types over the word size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179051 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 20:45:01 +00:00
Rafael Espindola
a9408bafcc Remove is64BitLoadCommand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179048 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 20:18:53 +00:00
Eli Bendersky
5fcba11b23 Rewrite test/Integer tests to use FileCheck instead of grep
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179047 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 20:18:15 +00:00
Eli Bendersky
20680b045a Rewrite test/ExecutionEngine tests to use FileCheck instead of grep
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179043 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 19:51:36 +00:00
Matt Arsenault
ed36a47867 Update documentation.
First feature is not CPU subtype anymore since r134127

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179038 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 18:52:58 +00:00
Eli Bendersky
c3d5c1cb33 Rewrite test/Verifier tests to use FileCheck instead of grep
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179036 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 18:33:51 +00:00
Arnold Schwaighofer
813456527e X86 cost model: Model cost for uitofp and sitofp on SSE2
The costs are overfitted so that I can still use the legalization factor.

For example the following kernel has about half the throughput vectorized than
unvectorized when compiled with SSE2. Before this patch we would vectorize it.

unsigned short A[1024];
double B[1024];
void f() {
  int i;
  for (i = 0; i < 1024; ++i) {
    B[i] = (double) A[i];
  }
}

radar://13599001

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179033 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 18:05:48 +00:00
Chad Rosier
6b369ceb58 [ms-inline asm] Add support for ImmDisp [ Symbol ] memory operands.
rdar://13521249


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 17:43:47 +00:00
Hal Finkel
5ee67e8e76 Generate PPC early conditional returns
PowerPC has a conditional branch to the link register (return) instruction: BCLR.
This should be used any time when we'd otherwise have a conditional branch to a
return. This adds a small pass, PPCEarlyReturn, which runs just prior to the
branch selection pass (and, importantly, after block placement) to generate
these conditional returns when possible. It will also eliminate unconditional
branches to returns (these happen rarely; most of the time these have already
been tail duplicated by the time PPCEarlyReturn is invoked). This is a nice
optimization for small functions that do not maintain a stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 16:24:03 +00:00
Alexey Samsonov
d6b89ef0fa DWARF parser: remove duplicated code and fix code style in DIE extractors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179023 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 14:37:16 +00:00
Rafael Espindola
9d55c099d6 Add all 4 MachO object types. Use the stored type to implement is64Bits().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179021 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 13:25:33 +00:00
Vincent Lejeune
bd7c634ab9 R600: Control Flow support for pre EG gen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179020 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-08 13:05:49 +00:00