Chris Lattner
3a9cfbaf86
Remove the debug machine code emitter. The "FilePrinterEmitter" is more
...
useful for debugging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28051 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-02 16:59:24 +00:00
Nate Begeman
cdf38c4edb
Extend printBasicBlockLabel a bit so that it can be used to print all
...
basic block labels, consolidating the code to do so in one place for each
target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28050 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-02 05:37:32 +00:00
Nate Begeman
5425267e84
Update the PPC compilation callback code to not need weird abi-violating
...
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28049 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-02 04:50:05 +00:00
Chris Lattner
b3674e4753
Add pass ID's for various passes, so they can be AddRequiredID. Patch by
...
Domagoj Babic!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28048 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-02 04:24:36 +00:00
Jeff Cohen
51b776d259
De-virtualize SwitchSection.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28047 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-02 03:58:45 +00:00
Jeff Cohen
c6a057b04d
De-virtualize EmitZeroes.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28046 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-02 03:46:13 +00:00
Jeff Cohen
4f1ea1e9d9
Finish support for Microsoft ML/MASM. May still be a few rough edges.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28045 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-02 03:11:50 +00:00
Jeff Cohen
c884db47f1
Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28044 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-02 01:16:28 +00:00
Chris Lattner
229924a79f
Fix a latent bug that my spiller patch last week exposed: we were leaving
...
instructions in the virtregfolded map that were deleted. Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map. The solution is to remove entries
from the map when we delete the instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28041 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 22:03:24 +00:00
Chris Lattner
8a18c13fa5
When promoting a load to a reg-reg copy, where the load was a previous
...
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28040 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 21:17:10 +00:00
Chris Lattner
35f2705e3d
Remove previous patch, which wasn't quite right.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28039 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 21:16:03 +00:00
Chris Lattner
de321a8014
Put PHI/INLINEASM into the correct namespace.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28037 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 17:00:49 +00:00
Evan Cheng
22608c2d1f
Dis-favor stores more
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28035 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 09:20:44 +00:00
Evan Cheng
f229a5d4be
Bottom up register-pressure reduction scheduler now pushes store operations
...
up the schedule. This helps code that looks like this:
loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...
Without this change, the stores and computations are more likely to
interleave:
loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...
This can increase the number of spills if we are unlucky.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28033 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 09:14:40 +00:00
Evan Cheng
3766d66b91
Didn't mean ScheduleDAGList.cpp to make the last checkin.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28030 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 08:56:34 +00:00
Evan Cheng
10dbd3ead8
Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28029 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 08:54:57 +00:00
Chris Lattner
99f2632b4b
Remove %'s from register names when in intel mode.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28027 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 05:53:50 +00:00
Chris Lattner
c80c43eee0
Format #APP lines a bit nicer
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28026 91177308-0d34-0410-b5e6-96231b3b80d8
2006-05-01 04:11:03 +00:00
Evan Cheng
200370fb56
Local spiller kills a store if the folded restore is turned into a copy.
...
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28024 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-30 08:41:47 +00:00
Jeff Cohen
10a59ce701
Mingw32 patches supplied by Anton Korobeynikov.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28023 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-29 18:41:44 +00:00
Chris Lattner
25c344a758
Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
...
with some changes I have to the new CFE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28022 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 23:33:20 +00:00
Evan Cheng
55c25f2a2f
I can't spell: Register, not Regsiter.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28021 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 23:19:39 +00:00
Evan Cheng
62f2700bcf
Implemented x86 inline asm b, h, w, k modifiers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28020 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 23:11:40 +00:00
Chris Lattner
94046b4d10
Fix InstCombine/2006-04-28-ShiftShiftLongLong.ll
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28019 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 22:21:41 +00:00
Chris Lattner
25b8b8cb2c
Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28017 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 21:56:10 +00:00
Evan Cheng
347d5f789a
Initial caller side support (for CCC only, not FastCC) of 128-bit vector
...
passing by value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28015 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 21:29:37 +00:00
Evan Cheng
3d48a90fbd
Bare-bone X86 inline asm printer support.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28014 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 21:19:05 +00:00
Evan Cheng
55d0fa1bfa
Remove the temporary option: -no-isel-fold-inflight
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28012 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 18:54:11 +00:00
Evan Cheng
43f3bd310b
Implement four-wide shuffle with 2 shufps if no more than two elements come
...
from each vector. e.g.
shuffle(G1, G2, 7, 1, 5, 2)
==>
movaps _G2, %xmm0
shufps $151, _G1, %xmm0
shufps $216, %xmm0, %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28011 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 07:03:38 +00:00
Chris Lattner
a0de843535
Fix PR743: emit -help output of a tool to cout, not cerr.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28010 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 05:36:25 +00:00
Evan Cheng
020c41f21e
TargetLowering::LowerArguments should return a VBIT_CONVERT of
...
FORMAL_ARGUMENTS SDOperand in the return result vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28009 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 05:25:15 +00:00
Chris Lattner
ba1fc3daf7
Mapping of physregs can make it so that the designated and input physregs are
...
the same. In this case, don't emit a noop copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28008 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 04:43:18 +00:00
Chris Lattner
ae74f55552
Fix Transforms/Reassociate/2006-04-27-ReassociateVector.ll
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28007 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 04:14:49 +00:00
Evan Cheng
ed1492eaf5
Use movaps instead of movapd for spill / restore.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28005 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 02:23:35 +00:00
Evan Cheng
552c4a8494
Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
...
node can be folded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28003 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 02:09:19 +00:00
Chris Lattner
addc55af6c
When we have a two-address instruction where the input cannot be clobbered
...
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy. This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write. As one example, this change does:
pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
xorps %XMM2, %XMM5
cmpltps %XMM1, %XMM0
- movaps XMMWORD PTR [%ESP + 52], %XMM0
- movapd %XMM6, XMMWORD PTR [%ESP + 52]
+ movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
movapd XMMWORD PTR [%ESP + 52], %XMM6
movaps %XMM6, %XMM0
cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
cmpltps %XMM3, %XMM0
- movaps XMMWORD PTR [%ESP + 20], %XMM0
- movapd %XMM7, XMMWORD PTR [%ESP + 20]
+ movaps %XMM7, %XMM0
cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
movapd XMMWORD PTR [%ESP + 20], %XMM7
cmpltps %XMM4, %XMM0
... which is far better than a store followed by a load!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28001 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 01:46:50 +00:00
Chris Lattner
e481e8bc8f
Add a note
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27999 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-28 00:04:05 +00:00
Chris Lattner
217fde5255
Add a note
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27998 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 21:40:57 +00:00
Chris Lattner
d929f06f4d
Add support for inserting undef into a vector. This implements
...
Transforms/InstCombine/vec_insert_to_shuffle.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27997 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 21:14:21 +00:00
Evan Cheng
fea89c14ec
Make x86 isel lowering produce tailcall nodes. They are match to normal calls
...
for now.
Patch contributed by Alexander Friedman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27994 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 08:40:39 +00:00
Evan Cheng
43824e8216
A couple of new entries.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27993 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 08:31:33 +00:00
Evan Cheng
2fdd95eee7
Support for passing 128-bit vector arguments via XMM registers.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27992 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 08:31:10 +00:00
Evan Cheng
f7179bb56e
Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
...
(VAND, VADD, etc.). Legalizer will assert otherwise.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27991 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 08:29:42 +00:00
Evan Cheng
5fb03ce905
Oops
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27989 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 05:44:50 +00:00
Evan Cheng
85e3800e42
Bug fix: not updating NumIntRegs.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27988 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 05:35:28 +00:00
Chris Lattner
a83385fb7b
Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and
...
PR748.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27987 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 05:01:07 +00:00
Evan Cheng
eda65fa20b
- Clean up formal argument lowering code. Prepare for vector pass by value work.
...
- Fixed vararg support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27985 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 01:32:22 +00:00
Chris Lattner
634c76c08c
Fix some nondeterminstic behavior in the mem2reg pass that (in addition to
...
nondeterminism being bad) could cause some trivial missed optimizations (dead
phi nodes being left around for later passes to clean up).
With this, llvm-gcc4 now bootstraps and correctly compares. I don't know
why I never tried to do it before... :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27984 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-27 01:14:43 +00:00
Chris Lattner
97156e7984
Implement Transforms/IndVarsSimplify/complex-scev.ll, a case where we didn't
...
recognize some simple affine IV's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27982 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-26 18:34:07 +00:00
Evan Cheng
9191dbba8e
Fix fastcc failures.
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27980 91177308-0d34-0410-b5e6-96231b3b80d8
2006-04-26 18:21:31 +00:00