Commit Graph

113050 Commits

Author SHA1 Message Date
Craig Topper
b8fa51de42 [X86] Remove two feature flags that covered sets of instructions that have no patterns or intrinsics. Since we don't check feature flags in the assembler parser for any instruction sets, these flags don't provide any value. This frees up 2 of the fully utilized feature flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228282 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 08:51:02 +00:00
Matt Arsenault
81eb6ca158 R600/SI: Fix i64 truncate to i1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228273 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 06:05:13 +00:00
Larisse Voufo
27fa7bdd07 Disable enumeral mismatch warning when compiling llvm with gcc.
Tested with gcc 4.9.2.
Compiling with -Werror was producing:
.../llvm/lib/Target/X86/X86ISelLowering.cpp: In function 'llvm::SDValue lowerVectorShuffleAsBitMask(llvm::SDLoc, llvm::MVT, llvm::SDValue, llvm::SDValue, llvm::ArrayRef<int>, llvm::SelectionDAG&)':
.../llvm/lib/Target/X86/X86ISelLowering.cpp:7771:40: error: enumeral mismatch in conditional expression: 'llvm::X86ISD::NodeType' vs 'llvm::ISD::NodeType' [-Werror=enum-compare]
   V = DAG.getNode(VT.isFloatingPoint() ? X86ISD::FAND : ISD::AND, DL, VT, V,
                                        ^

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228271 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 04:54:51 +00:00
Matt Arsenault
0ac74cc4e3 Add addrspacecast node to tablegen
The node is still defined oddly so that the
address spaces are not operands and not accessible
from tablegen, but as-is this can now be used to write
a ComplexPattern with an addrspacecast root node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228270 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 03:35:34 +00:00
Matt Arsenault
7575430de4 Add support for double / float to EndianStream
Also add new unit tests for endian::Writer

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228269 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 03:30:08 +00:00
Michael Zolotukhin
710ce5d36b Implement new heuristic for complete loop unrolling.
Complete loop unrolling can make some loads constant, thus enabling a
lot of other optimizations. To catch such cases, we look for loads that
might become constants and estimate number of instructions that would be
simplified or become dead after substitution.

Example:
Suppose we have:
int a[] = {0, 1, 0};
v = 0;
for (i = 0; i < 3; i ++)
  v += b[i]*a[i];

If we completely unroll the loop, we would get:
v = b[0]*a[0] + b[1]*a[1] + b[2]*a[2]

Which then will be simplified to:
v = b[0]* 0 + b[1]* 1 + b[2]* 0

And finally:
v = b[1]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228265 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 02:34:00 +00:00
Cameron Esfahani
d02540a1d7 Value soft float calls as more expensive in the inliner.
Summary: When evaluating floating point instructions in the inliner, ask the TTI whether it is an expensive operation.  By default, it's not an expensive operation.  This keeps the default behavior the same as before.  The ARM TTI has been updated to return back TCC_Expensive for targets which don't have hardware floating point.

Reviewers: chandlerc, echristo

Reviewed By: echristo

Subscribers: t.p.northover, aemerson, llvm-commits

Differential Revision: http://reviews.llvm.org/D6936

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228263 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 02:09:33 +00:00
Ahmed Bougacha
a7f2cf45f3 [ARM] Use patterns instead of hardcoded regs in test. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228259 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 01:52:19 +00:00
Ahmed Bougacha
42ec3433ef [ARM] Make testcase more explicit. NFC.
The q8/d16 thing is silly;  I'd be happy to hear about a better
way to write those tests where simple substitution isn't enough..


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228258 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 01:45:28 +00:00
Reid Kleckner
6d3ceb23c7 Try to fix the build in MCValue.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228256 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 01:23:14 +00:00
Sean Silva
bd59cd48d5 Fixup.
Didn't see these calls in my release build locally when testing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228254 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 01:13:47 +00:00
Duncan P. N. Exon Smith
c760eff69f IR: Split out getOperandAs(), NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228250 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 01:07:47 +00:00
Sean Silva
a875e3d4d6 [MC] Remove various unused MCAsmInfo parameters.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228244 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 00:58:51 +00:00
Duncan P. N. Exon Smith
09b44e9be7 IR: Rename 'operator ==()' to 'isKeyOf()', NFC
`isKeyOf()` is a clearer name than overloading `operator==()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228242 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 00:51:35 +00:00
Duncan P. N. Exon Smith
97ec768f7f ADT: Add int64_t interoperability to APSInt
Add some API to `APSInt` to make it easier to compare with `int64_t`.

  - `APSInt::compareValues(APSInt, APSInt)` returns 1, -1 or 0 for
    greater, lesser, or equal, doing the right thing for mismatched
    "has-sign" and bitwidths.  This is just like `isSameValue()` (and is
    now the implementation of it).
  - `APSInt::get(int64_t)` gets a signed `APSInt`.
  - `operator<(int64_t)`, etc., are implemented trivially via `get()`
    and `compareValues()`.
  - Also added `APSInt::getUnsigned(uint64_t)` to make it easier to test
    `compareValues()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228239 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 00:17:43 +00:00
Colin LeMahieu
91568ff3aa [Hexagon] Deleting unused instructions and adding isCodeGenOnly to some defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228238 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-05 00:10:16 +00:00
Colin LeMahieu
69a33e427e [Hexagon] Updating load extend to i64 patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228237 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 23:55:16 +00:00
Kostya Serebryany
5d85a10810 [fuzzer] add flag prefer_small_during_initial_shuffle, be a bit more verbose
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228235 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 23:42:42 +00:00
Colin LeMahieu
2747f4aaf5 [Hexagon] Cleaning up i1 load and extension patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228232 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 23:27:48 +00:00
Colin LeMahieu
083cc71ab3 [Hexagon] Simplifying more load and store patterns and using new addressing patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228231 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 23:23:16 +00:00
Reid Kleckner
cfa2c32166 Remove useless call to isOSCygMing()
This used to do something when we modeled the Cygwin and MinGW
environments as distinct OSs, but now it is not needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228229 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 23:17:19 +00:00
Tom Stellard
26bfda9dd3 R600/SI: Enable subreg liveness by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228228 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 23:14:18 +00:00
Colin LeMahieu
18c8166405 [Hexagon] Simplifying some load and store patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228227 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 23:10:21 +00:00
Duncan P. N. Exon Smith
783e0e4b23 AsmParser: Split out LineField, NFC
Split out `LineField`, which restricts the legal line numbers.  This
will make it easier to be consistent between different node parsers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228226 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:59:18 +00:00
Colin LeMahieu
82bc37ed90 [Hexagon] Converting absolute-address load patterns to use AddrGP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228225 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:54:51 +00:00
Colin LeMahieu
0f9cf365b2 [Hexagon] Converting atomic store/load to use AddrGP addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228223 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:40:36 +00:00
Reid Kleckner
304821b21b Don't warn or note if bash is missing
We haven't needed bash on Windows to run the test suite for a long time
now.

Patch by Michael Edwards!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228221 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:36:52 +00:00
Colin LeMahieu
243f011835 [Hexagon] Simplifying some store patterns. Adding AddrGP addressing forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228220 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:36:28 +00:00
Filipe Cabecinhas
cec4461c47 Handle LLVM_USE_SANITIZER=Address;Undefined (and the other way around)
Summary:
Handle LLVM_USE_SANITIZER=Address;Undefined to enable ASan and UBSan
If UBSan is compatible with more of the other sanitizers, maybe we should
deal with this in a better way where we allow combining UBSan with any of
the other sanitizers.

Reviewers: samsonov

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D7024

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228219 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:33:31 +00:00
Kostya Serebryany
46c638cfc8 [fuzzer] add -runs=N to limit the number of runs per session. Also, make sure we do some mutations w/o cross over.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228214 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:20:09 +00:00
Duncan P. N. Exon Smith
8054a41a27 Fix GCC error caused by r228211
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228213 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:13:28 +00:00
Duncan P. N. Exon Smith
890324873f IR: Reduce boilerplate in DenseMapInfo overrides, NFC
Minimize the boilerplate required for the `MDNode` subclass
`DenseMapInfo<>` overrides in `LLVMContextImpl`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228212 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:08:30 +00:00
Duncan P. N. Exon Smith
89aee384c1 AsmParser: Move MDField details to source file, NFC
Move all the types of `MDField` to an anonymous namespace in the source
file.  This also eliminates the duplication of `ParseMDField()`
declarations in the header for each new field type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228211 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:05:21 +00:00
Duncan P. N. Exon Smith
99dc945c08 AsmParser: Simplify assertion, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228209 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:02:18 +00:00
Duncan P. N. Exon Smith
7ec73f04a8 AsmParser: Remove dead code, NFC
This condition is checked in the generic `ParseMDField()`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228208 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 22:00:59 +00:00
Duncan P. N. Exon Smith
321b43e7cc AsmParser: Simplify MDUnsignedField
We only need `uint64_t` for storage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228205 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 21:57:52 +00:00
Duncan P. N. Exon Smith
ab47b42e26 IR: Initialize MDNode abbreviations en masse, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228203 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 21:54:12 +00:00
Duncan P. N. Exon Smith
a196629a7c IR: Define MDNode uniquing sets automatically, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228200 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 21:46:12 +00:00
Kevin Enderby
3cc1e2deee Add code to llvm-objdump so the -section option with -macho will dump ‘C’ string
sections with the Mach-O S_CSTRING_LITERALS section type.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228198 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 21:38:42 +00:00
Rafael Espindola
e247dd2839 Don' try to make sections in comdats SHF_MERGE.
Parts of llvm were not expecting it and we wouldn't print
the entity size of the section.

Given what comdats are used for, having SHF_MERGE sections would be
just a small improvement, so just disable it for now.

Fixes pr22463.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228196 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 21:27:24 +00:00
Sean Silva
54a6137379 [docs] Put an explicit link to InAlloca.rst
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228192 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:51:19 +00:00
Tom Stellard
89c96b1cd0 R600/SI: Expand misaligned 16-bit memory accesses
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228190 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:49:52 +00:00
Tom Stellard
fd4c349de2 R600/SI: Make more store operations legal
v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for
all address spaces.  We had marked them as custom in order to lower
them for the private address space, but this is no longer necessary.

This enables lowering of misaligned stores of these types in the
DAGLegalizer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228189 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:49:51 +00:00
Tom Stellard
056a34916a R600: Don't promote i64 stores to v2i32 during DAG legalization
We take care of this during instruction selection now.  This
fixes a potential infinite loop when lowering misaligned stores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228188 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:49:49 +00:00
Tom Stellard
f22ee14444 StructurizeCFG: Remove obsolete fix for loop backedge detection
This is no longer needed now that we are using a reverse post-order
traversal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228187 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:49:47 +00:00
Tom Stellard
7c038bc15f StructurizeCFG: Use a reverse post-order traversal
We were previously doing a post-order traversal and operating on the
list in reverse, however this would occasionaly cause backedges for
loops to be visited before some of the other blocks in the loop.

We know use a reverse post-order traversal, which avoids this issue.

The reverse post-order traversal is not completely ideal, so we need
to manually fixup the list to ensure that inner loop backedges are
visited before outer loop backedges.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228186 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:49:44 +00:00
Colin LeMahieu
1d75b286e6 [Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load patterns to make use of them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228184 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:38:01 +00:00
Bill Schmidt
b9fc61d031 Add missing test case from r228046
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228182 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 20:00:04 +00:00
Duncan P. N. Exon Smith
a7a6be22eb Utils: Resolve cycles under distinct MDNodes
Track unresolved nodes under distinct `MDNode`s during `MapMetadata()`,
and resolve them at the end.  Previously, these cycles wouldn't get
resolved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228180 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 19:44:34 +00:00
Matthias Braun
a602c10686 MachineCSE: Clear dead-def flag on CSE.
In case CSE reuses a previoulsy unused register the dead-def flag has to
be cleared on the def operand, as exposed by the arm64-cse.ll test.

This fixes PR22439 and the corresponding rdar://19694987

Differential Revision: http://reviews.llvm.org/D7395

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228178 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-04 19:35:16 +00:00