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8279 Commits

Author SHA1 Message Date
Chad Rosier
3fb6eca0cd Tidy up naming for consistency and other cleanup. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157358 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-23 23:45:10 +00:00
Craig Topper
88097819fc Tidy up spacing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157313 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-23 05:44:51 +00:00
Craig Topper
82dd67a1c8 Fix indentation of wrapped line for readability. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157309 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-23 03:59:53 +00:00
Craig Topper
85b9e56bac Fix constant used for pshufb mask when lowering v16i8 shuffles. Bug introduced in r157043. Fixes PR12908. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157236 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-22 06:09:38 +00:00
Craig Topper
8ae97baef2 Allow 256-bit shuffles to still be split even if only half of the shuffle comes from two 128-bit pieces. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157175 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-21 06:40:16 +00:00
Jakob Stoklund Olesen
53df9259e9 Make the global base reg GR32_NOSP. 
It can sometimes be used in addressing modes that don't support %ESP.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157165 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-20 18:43:00 +00:00
Nadav Rotem
87d35e8c71 On Haswell, perfer storing YMM registers using a single instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157129 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-19 20:30:08 +00:00
Nadav Rotem
4fc8a5de44 Add support for additional in-reg vbroadcast patterns 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157127 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-19 19:57:37 +00:00
Craig Topper
5084c6b0a2 Tidy up some spacing and inconsistent use of pre/post increment. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-19 19:14:18 +00:00
Craig Topper
769237bb92 Copy some AVX support from MCJIT to JIT. Maybe will fix PR12748. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157109 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-19 08:28:17 +00:00
Jim Grosbach
3e96531186 Refactor data-in-code annotations. 
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.

Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.

data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"

The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.

rdar://11459456

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157062 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-18 19:12:01 +00:00
Craig Topper
be97ae9e89 Simplify code a bit. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-18 07:07:36 +00:00
Craig Topper
b82b5abf78 Simplify handling of v16i8 shuffles and fix a missed optimization. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157043 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-18 06:42:06 +00:00
Evan Cheng
6100366c2f Avoid creating a cycle when folding load / op with flag / store. PR11451474. rdar://11451474 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156896 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-16 01:54:27 +00:00
Jim Grosbach
918f55fe23 Allow MCCodeEmitter access to the target MCRegisterInfo. 
Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-15 17:35:52 +00:00
Dan Gohman
a6063c6e29 Rename @llvm.debugger to @llvm.debugtrap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-14 18:58:10 +00:00
Chad Rosier
e1093e5503 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156633 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:43:29 +00:00
Preston Gurd
3c579c8343 Added X86 Atom latencies to X86InstrMMX.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 14:27:12 +00:00
Hans Wennborg
228756c744 Implement initial-exec TLS model for 32-bit PIC x86 
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 10:11:01 +00:00
Dan Gohman
d4347e1af9 Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(), 
but it generates int3 on x86 instead of ud2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 00:19:32 +00:00
Preston Gurd
deaa3f3e52 Added X86 Atom latencies for instructions in X86InstrInfo.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:58:35 +00:00
Nadav Rotem
b88e8dd31d Fix merge-typo and cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156541 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 12:50:02 +00:00
Nadav Rotem
b210651654 AVX2: Add an additional broadcast idiom. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156540 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 12:39:13 +00:00
Nadav Rotem
5fc2187a02 Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in the program. 
Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users.

Fix PR11900.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156539 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 12:22:05 +00:00
Jakob Stoklund Olesen
cf661a040c Use ptr_rc_tailcall instead of GR32_TC. 
The getPointerRegClass() hook will return GR32_TC, or whatever is
appropriate for the current function.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 01:50:09 +00:00
Jakob Stoklund Olesen
1910cb1e3d s/CSR_Ghc/CSR_NoRegs/ 
Share the CalleeSavedRegs defs between all calling conventions having no
callee-saved registers.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156382 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-08 15:07:29 +00:00
Craig Topper
189bce48c7 Remove 256-bit AVX non-temporal store intrinsics. Similar was previously done for 128-bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156375 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-08 06:58:15 +00:00
Jakob Stoklund Olesen
397fc4874e Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156328 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 22:10:26 +00:00
Chad Rosier
42726835e3 Fix a regression from r147481. This combine should only happen if there is a 
single use.
rdar://11360370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156316 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 18:47:44 +00:00
Manman Ren
ed57984483 X86: optimization for -(x != 0) 
This patch will optimize -(x != 0) on X86
FROM 
cmpl	$0x01,%edi
sbbl	%eax,%eax
notl	%eax
TO
negl %edi
sbbl %eax %eax

In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td:
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;

rdar: 10961709


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156312 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 18:06:23 +00:00
Craig Topper
ef2b8bda02 Fix some issues in the f16c instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 06:00:15 +00:00
Craig Topper
5f9cccc509 Add SSE4A MOVNTSS/MOVNTSD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156281 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-07 05:36:19 +00:00
Craig Topper
d978c54e60 Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156268 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-06 19:46:21 +00:00
Craig Topper
bdcbcb3ae7 Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156266 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-06 18:54:26 +00:00
Craig Topper
156f5bb56e Add shuffle decode support for VPERMQ/VPERMPD. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156265 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-06 18:44:02 +00:00
Jim Grosbach
e5f31ad55e Nuke a few dead remnants of the CBE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156241 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-05 17:45:12 +00:00
Benjamin Kramer
aaf723dd2b Add a new target hook "predictableSelectIsExpensive". 
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.

Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.

I'm not entirely happy with the name of this flag, suggestions welcome ;)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156233 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-05 12:49:14 +00:00
Preston Gurd
3d142e58ef Adds Intel Atom scheduling latencies to X86InstrSystem.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156194 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 19:26:37 +00:00
Craig Topper
31a207a3b7 Fix some loops to match coding standards. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156159 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 06:39:13 +00:00
Craig Topper
6643d9c180 Fix up some spacing. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156158 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 06:18:33 +00:00
Craig Topper
5da8a80377 Simplify broadcast lowering code. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156157 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 05:49:51 +00:00
Craig Topper
f3640d7ec1 Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156156 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 04:44:49 +00:00
Craig Topper
11ac1f81a8 Simplify shuffle narrowing code a bit. No functional change intended. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156154 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 04:08:44 +00:00
Jakob Stoklund Olesen
338607ae0d Remove the SubRegClasses field from RegisterClass descriptions. 
This information in now computed by TableGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-04 03:30:34 +00:00
Craig Topper
b607264550 Use 'unsigned' instead of 'int' in a few places dealing with counts of vector elements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156060 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 07:26:59 +00:00
Craig Topper
6b28d356c5 Fix 256-bit vpshuflw and vpshufhw immediate encoding to handle undefs in the lower half correctly. Missed in r155982. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156059 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-03 07:12:59 +00:00
Preston Gurd
c0f0a93936 For Intel Atom, use ILP scheduling always, instead of ILP for 64 bit 
and Hybrid for 32 bit, since benchmarks show ILP scheduling is better
most of the time.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156028 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 22:02:02 +00:00
Preston Gurd
79bbe855cd Change the Intel Atom detection code to recognize 
Lincroft and Medfield.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 21:38:46 +00:00
Preston Gurd
95f0cf0438 This patch continues the work of adding instruction latencies for X86 Atom, 
by providing the latencies for the instructions in X86InstrFPStack.td.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155996 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 16:03:35 +00:00
Manman Ren
e2849851b2 Revert r155853 
The commit is intended to fix rdar://10961709.
But it is the root cause of PR12720.
Revert it for now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155992 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-02 15:24:32 +00:00