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47aa9a2bb5
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22582 Commits

Author SHA1 Message Date
Bill Wendling
47aa9a2bb5 Make sure we add the predicate after all of the registers are added. 
<rdar://problem/12183003>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 22:12:44 +00:00
Craig Topper
1d90bbba14 Remove MMX shift intrinsic handling code that also exists in SelectionDAGBuilder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162661 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 08:08:30 +00:00
Craig Topper
58bfb27c4b Don't allow vextractf128 to be folded with unaligned stores. We don't fold unaligned loads so shouldn't fold unaligned stores as it can cause an alignment fault to occur. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162658 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 07:19:59 +00:00
Craig Topper
903090c55e Fold some patterns into instruction definitons so tablegen can infer flags removing the need for an explicit 'neverHasSideEffects = 1' 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162656 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 07:04:50 +00:00
Craig Topper
3a1683f88f Add HasAVX1Only predicate and use it for patterns that have an AVX1 instruction and an AVX2 instruction rather than relying on AddedComplexity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162654 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-27 06:08:57 +00:00
Richard Smith
1144af3c9b Fix integer undefined behavior due to signed left shift overflow in LLVM. 
Reviewed offline by chandlerc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 23:29:28 +00:00
Jakob Stoklund Olesen
cac59d8ae8 Add missing mayLoad flags to a large class of AVX *_Int instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162622 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 23:29:07 +00:00
Jakob Stoklund Olesen
36ff8f25c5 Missed tLEApcrelJT. 
ARMConstantIslandPass expects this instruction to stay in the same basic
block as the jump table branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162615 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 22:46:55 +00:00
Jakob Stoklund Olesen
7778ee1ed9 Explicitly mark LEApcrel pseudos with hasSideEffects. 
It's not clear that they should be marked as such, but tbb formation
fails if t2LEApcrelJT is hoisted of of a loop.

This doesn't change the flags on these instructions,
UnmodeledSideEffects was already inferred from the missing pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162603 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 21:44:11 +00:00
Jakob Stoklund Olesen
0745b649ed Fix call instruction operands in ARMFastISel. 
The ARM BL and BLX instructions don't have predicate operands, but the
thumb variants tBL and tBLX do.

The argument registers should be added as implicit uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162593 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 20:52:46 +00:00
Jakob Stoklund Olesen
9511a460d8 Mark X86::RET and RETI instructions as variadic. 
There is special magic happening when returning floating point values on
the x87 stack. The RET instructions get extra f80 operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162592 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 20:52:44 +00:00
Akira Hatanaka
16865d0612 Disable Mips' delay slot filler when optimization level is O0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162589 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 20:40:15 +00:00
Akira Hatanaka
45d8dbc92d In MipsDAGToDAGISel::SelectAddr, fold add node into address operand, if its 
second operand is MipsISD::GPRel.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162584 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 20:21:49 +00:00
Roman Divacky
9fb8b49380 Lower constant pools and jump tables via TOC on PPC64/SVR4. 
In collaboration with Adhemerval Zanella.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 16:26:02 +00:00
Jakob Stoklund Olesen
4d320db5d1 Fix load/store SDNode flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162558 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 14:43:30 +00:00
Jakob Stoklund Olesen
ea47628cba Add missing SDNPSideEffect flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162557 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 14:43:27 +00:00
Jakob Stoklund Olesen
3d2a2d1217 Remove more mayLoad workarounds. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 14:43:22 +00:00
Craig Topper
0e292376d0 Custom lower FMA intrinsics to target specific nodes and remove the patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162534 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 04:03:22 +00:00
Richard Smith
aaf217953b Fix undefined behavior (negation of INT_MIN) in ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162520 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 00:35:46 +00:00
Jakob Stoklund Olesen
6211386799 Remove some spurious mayLoad = 0 flags. 
They were inserted to silence TableGen's warning about
redundant properties. That warning is now gone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162517 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 00:31:20 +00:00
Jakob Stoklund Olesen
02c63803e5 Add missing SDNP properties on the flushw node. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162515 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 00:31:13 +00:00
Jakob Stoklund Olesen
cfe8a9695b X86MemBarrier has unmodeled side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162514 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-24 00:31:10 +00:00
Jakob Stoklund Olesen
91f3a6cfd9 Preserve operand flags in convertToThreeAddress() by copying operands. 
No test case, this is a generalization of r160260.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162485 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-23 22:36:31 +00:00
Craig Topper
9b54141cae Favor FMA3 over FMA4 if both are enabled. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162454 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-23 18:14:30 +00:00
Craig Topper
8a5bc5ad90 Use a switch statement instead of a bunch of if-else checks and pull out the common function call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162428 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-23 04:57:36 +00:00
Craig Topper
71eab96bfd Remove unused private field to silence build warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162426 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-23 04:45:31 +00:00
Akira Hatanaka
fc4eafa0f4 Make function loadImmediate a member of MipsSEInstrInfo and change it to return 
the temporary register that was used to load the immediate. Currently, it always
returns register $at, but this will change if, in the future, we decide to use 
another register.

No changes in functionality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162417 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-23 00:21:05 +00:00
Akira Hatanaka
91a35f03da Add a member of type Mips16InstrInfo/MipsSEInstrInfo to class 
Mips16RegisterInfo/MipsSERegisterInfo. 

No changes in functionality.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162413 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 23:58:53 +00:00
Chad Rosier
674101e6bb [ms-inline asm] Avoid a false positive assertion 
Assertion failed: (Start.isValid() == End.isValid() && "Start and end should 
either both be valid or both be invalid!")

when parsing inline asm.  SMLoc assumes that the first char * in the source is
invalid.  However, when parsing an inline asm the mnemonic is at this location.
I don't want to change SMLoc, so use a trivial workaround.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162381 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 19:14:29 +00:00
Benjamin Kramer
05d96f98cb Reduce duplicated hash map lookups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162362 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 15:37:57 +00:00
Craig Topper
96601ca332 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162347 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 06:07:19 +00:00
Craig Topper
df8de92083 Don't cache the MBB in the class. Its only used by one function. Change a for loop over operands to use unsigned instead of int. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162344 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 05:59:59 +00:00
Craig Topper
f7c4d26f77 Mark a function as static since it doesn't use anything in the class. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162342 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 05:36:44 +00:00
Akira Hatanaka
e7338cd550 Add register Mips::GP to the list of reserved registers if target is bare-metal 
to prevent it from being clobbered. mips uses $gp to access small data section.

This bug was originally reported by Carl Norum.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162340 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 03:18:13 +00:00
Akira Hatanaka
6522a9e04b Add option disable-mips-delay-filler. Turn on mips' delay slot filler by 
default.

Patch by Carl Norum.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162339 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 02:51:28 +00:00
Jack Carter
101771ba4d For mips64 switch statements in subroutines could generate 
within the codegen EK_GPRel64BlockAddress. This was not 
supported for direct object output and resulted in an assertion.

This change adds support for EK_GPRel64BlockAddress for 
direct object.

One fallout from this is to turn on rela relocations 
for mips64 to match gas.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162334 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-22 00:49:30 +00:00
Chad Rosier
6871d1eceb Add a few functions to TargetLibraryInfo as part of PR13574. 
Patch by Weiming Zhao <weimingz@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162329 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 23:28:56 +00:00
Richard Smith
fca01b5e2b Fix unaligned memory accesses when performing relocations in X86 JIT. There's 
no cost to using memcpy here: the fixed code is optimized by LLVM to perfect
machine code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162311 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 20:48:36 +00:00
Chad Rosier
b4fdadef51 [ms-inline asm] Do not report a Parser error when matching inline assembly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162306 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 19:36:59 +00:00
Chad Rosier
64bfcbbc58 [ms-inline asm] Expose the ErrorInfo from the MatchInstructionImpl. In general, 
this is the index of the operand that failed to match.

Note: This may cause a buildbot failure due to an API mismatch in clang.  Should
recover with my next commit to clang.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162295 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 18:14:59 +00:00
Craig Topper
4dea906e1a Fix up indentation and remove a couple else's after returns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162270 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 08:29:51 +00:00
Craig Topper
a182367e59 Use uint16_t for tables of opcodes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162267 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 08:23:21 +00:00
Craig Topper
630e33a857 Fix up indentation. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162264 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 08:17:07 +00:00
Craig Topper
195f1b8a26 Add a couple llvm_unreachables. Add a message to several others. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162263 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 08:16:16 +00:00
Craig Topper
cba48d8c05 Replace a break with llvm_unreachable in the default case of a nested switch. Condense code a bit. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162261 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 07:32:16 +00:00
Craig Topper
5f67d94697 Cleanup the scalar FMA3 definitions. Add patterns to fold loads with scalar forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162260 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 07:11:11 +00:00
Craig Topper
e4b6189658 Merge FMA3 instructions with and without patterns into single classes using null_frag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162257 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 05:56:45 +00:00
Jakob Stoklund Olesen
5379904807 Add a missing def flag. 
*** Bad machine code: Explicit definition marked as use ***
- function:    test_cos
- basic block: BB#0 L.entry (0x7ff2a2024fd0)
- instruction: VSETLNi32 %D11, %D11<undef>, %R0, 0, pred:14, pred:%noreg, %Q5<imp-use,kill>, %Q5<imp-def>
- operand 0:   %D11

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162247 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-21 00:34:53 +00:00
Jakob Stoklund Olesen
a0708d1109 Use a SmallPtrSet to dedup successors in EmitSjLjDispatchBlock. 
The test case ARM/2011-05-04-MultipleLandingPadSuccs.ll was creating
duplicate successor list entries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162222 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-20 20:52:03 +00:00
Sebastian Pop
b72a939d8d fix HexagonSubtarget parsing of -mv flag 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162217 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-08-20 19:56:47 +00:00