Chris Lattner
a7f1354eb5
fix rdar://7986634 - match instruction opcodes case insensitively.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104183 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:34:33 +00:00
Bill Wendling
a008750aa9
Testcase for r104181.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104182 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 23:33:26 +00:00
Eric Christopher
591466baff
A more combo tls testcase.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104163 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 21:19:42 +00:00
Eric Christopher
aa6c72ec95
Few more simple tls testcases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104148 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:35:15 +00:00
Jakob Stoklund Olesen
3437352887
TwoAddressInstructionPass doesn't really know how to merge live intervals when
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lowering REG_SEQUENCE instructions.
Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 20:08:00 +00:00
Eric Christopher
d38bbfadfd
Attempt to run this test on x86 only.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104143 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 18:59:37 +00:00
Bob Wilson
29e7e32e08
Testcase to go with 104141.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104142 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 18:58:37 +00:00
Evan Cheng
9085f98b32
t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 07:28:01 +00:00
Evan Cheng
0a942dbb1e
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
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The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 01:08:17 +00:00
Eric Christopher
cc6b6b9348
Add a test to make sure that we're lowering the shift amount correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104090 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-19 00:22:04 +00:00
Jakob Stoklund Olesen
dcf7708ad9
Remember to update VirtRegLastUse when spilling without killing before a call.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104074 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 22:20:09 +00:00
Dan Gohman
e5efbafdac
When converting a test to a cmp to fold a load, use the cmp that has an
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8-bit immediate field rather than one with a wider immediate field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:42:03 +00:00
Eric Christopher
b4e876e37e
Quick test to make sure we're emitting the tbss section correctly.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104063 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:40:20 +00:00
Evan Cheng
28dad2a5ca
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104060 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 21:31:17 +00:00
Dale Johannesen
0182fa2e38
Test passed on ppc, to my surprise; if it worked
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there it may work everywhere...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104053 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:47:04 +00:00
Evan Cheng
27e4840e03
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 20:03:28 +00:00
Dale Johannesen
f336bea195
Testcase for llvm-gcc checkin 104042.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104043 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 19:03:51 +00:00
Kevin Enderby
d8ba292c9b
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
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correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:51:35 +00:00
Daniel Dunbar
2ae4bfd769
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
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Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104033 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:28:24 +00:00
Daniel Dunbar
3f40b31256
MC/X86: Implement custom lowering to make sure we match things like
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X86::ADC32ri $0, %eax
to
X86::ADC32i32 $0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104030 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 17:22:24 +00:00
Evan Cheng
a083988c8a
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104004 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 00:03:40 +00:00
Evan Cheng
c6dcce3ba5
Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:24:12 +00:00
Kevin Enderby
ebe7fcd041
Added support in MC for Directional Local Labels.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103989 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 23:08:19 +00:00
Eric Christopher
c6177a4531
More data/parsing support for tls directives. Add a few more testcases
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and cleanup comments as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103985 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 22:53:55 +00:00
Evan Cheng
44bfdd3d78
Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103984 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 22:09:49 +00:00
Daniel Dunbar
648ac5153e
MC/Mach-O/x86: Optimal nop sequences should only be used for the .text sections, not all sections in the text segment.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103981 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:54:30 +00:00
Daniel Dunbar
db9014dd8b
MC/Mach-O: Reverse order of SymbolData scanning when emitting instructions.
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- This fixes a string table mismatch with 'as' when two new symbols are defined
in a single instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103979 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 21:19:59 +00:00
Evan Cheng
53c779bb3a
Careful with reg_sequence coalescing to not to overwrite sub-register indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103971 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:57:12 +00:00
Daniel Dunbar
b18d2dd115
MC/Mach-O: Fix some differences in symbol flag handling.
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- Don't clear weak reference flag, 'as' was only "trying" to do this, it wasn't
actually succeeding.
- Clear the "lazy bound" bit when we mark something external. This corresponds
roughly to the lazy clearing of the bit that 'as' implements in
symbol_table_lookup.
- The exact meaning of these flags appears pretty loose, since 'as' isn't very
consistent. For now we just try to match 'as', we will clean this up one day
hopefully.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103964 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 20:12:31 +00:00
Evan Cheng
6206124250
Turn on -neon-reg-sequence by default.
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Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103960 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 19:51:20 +00:00
Daniel Dunbar
525a3a67c1
llvm-mc: Support reassignment of variables in one special case, when the
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variable has not yet been used in an expression. This allows us to support a few
cases that show up in real code (mostly because gcc generates it for Objective-C
on Darwin), without giving up a reasonable semantic model for assignment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 17:46:23 +00:00
Jakob Stoklund Olesen
aa4b0159da
Avoid allocating the same physreg to multiple virtregs in one instruction.
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While that approach works wonders for register pressure, it tends to break
everything.
This should unbreak the arm-linux builder and fix a number of miscompilations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103946 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 17:18:59 +00:00
Jakob Stoklund Olesen
0c9e4f5f3f
Only use clairvoyance when defining a register, and then only if it has one use.
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This makes allocation independent on the ordering of use-def chains.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103935 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 04:50:57 +00:00
Eric Christopher
d04d98d24f
Assume that we'll handle mangling the symbols earlier and just put the
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symbol to the file as we have it. Simplifies out tbss handling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103928 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-17 02:13:02 +00:00
Dale Johannesen
88dc976102
Removing as part of previous reversion.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103915 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 20:19:40 +00:00
Dale Johannesen
f7f5a2760a
Revert 103911; it broke a test that expects bitconvert
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<1xi64> -> i64 to work in MMX registers on hosts where -no-sse
is the default (not mine). The right thing is
to accept this and make i64->f64 conversions go through memory,
but I don't have time right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103914 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 20:19:04 +00:00
Dale Johannesen
f9b2242927
Make x86-64 64-bit bitconvert work when SSE is not available.
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(This worked as of about 6 months ago and I didn't track down
exactly what broke it; I think this fix is appropriate.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103911 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 18:22:38 +00:00
Anton Korobeynikov
ded05e34b6
Add support for thiscall calling convention.
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Patch by Charles Davis and Steven Watanabe!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103902 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-16 09:08:45 +00:00
Anton Korobeynikov
a9790d739a
Some cheap DAG combine goodness for multiplication with a particular constant.
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This can be extended later on to handle more "complex" constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 18:16:59 +00:00
Evan Cheng
06b666c705
Allow TargetLowering::getRegClassFor() to be called on illegal types. Also
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allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103854 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:18:07 +00:00
Bill Wendling
23ead99283
SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and
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replace the check with the appropriate predicate. Modify the testcase to reflect
the correct code. (It should be saving callee-saved registers on the stack
allocated by the calling fuction.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103829 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 22:17:42 +00:00
Devang Patel
552b888744
Test case for r103800.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103801 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 21:04:45 +00:00
Kevin Enderby
c3ce05c594
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an
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argument, like "int $4", to not get an Assertion error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 19:16:02 +00:00
Daniel Dunbar
f0f6cdb6b4
MC/Mach-O/x86_64: Darwin's special "signed_N" relocation types should only be
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used to replace a normal relocation, not a reference to a GOT entry.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103789 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 18:53:40 +00:00
Jakob Stoklund Olesen
4ed1082683
Simplify the handling of physreg defs and uses in RegAllocFast.
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This adds extra security against using clobbered physregs, and it adds kill
markers to physreg uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103784 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 18:03:25 +00:00
Daniel Dunbar
bd616b69f7
XFAIL the test I added with vg_leak, apparently it is the first and only llc
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-filetype=obj test, and -filetype=obj leaks a few objects. Added a FIXME, we
need to sort out the ownership model for the various MC objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103769 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 07:47:51 +00:00
Daniel Dunbar
d11d59e35a
Inline Asm: Ensure buffer is newline terminated to match how the text is printed.
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- This is a hack, but I can't decide the best place to handle this. Chris?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103765 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 04:31:50 +00:00
Eric Christopher
482eba054a
Add AsmParser support for darwin tbss directive.
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Nothing uses this yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103757 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 01:50:28 +00:00
Nick Lewycky
eb7d818969
Actually run the test. Thanks Daniel Dunbar!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103720 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 17:41:06 +00:00
Nick Lewycky
12b927bad0
Add testcase for r103653.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103699 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 06:00:14 +00:00