Commit Graph

5815 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
4964ba01f9 Use getRegForValue() to materialize the address of ARM globals.
This enables basic local CSE, giving us 20% smaller code for
consumer-typeset in -O0 builds.

<rdar://problem/10658692>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147720 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 04:07:22 +00:00
Evan Cheng
ccec74738d Copy implicit defs (e.g. r0) when changing tBX_RET to tPOP_RET. This bug is
exposed with an upcoming change will would delete the copy to return register
because there is no use! It's amazing anything works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147715 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 02:55:54 +00:00
Jakob Stoklund Olesen
45ca7c6336 Use movw+movt in ARMFastISel::ARMMaterializeGV.
This eliminates a lot of constant pool entries for -O0 builds of code
with many global variable accesses.

This speeds up -O0 codegen of consumer-typeset by 2x because the
constant island pass no longer has to look at thousands of constant pool
entries.

<rdar://problem/10629774>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-07 01:47:05 +00:00
Jakob Stoklund Olesen
bad1e6b8e0 Enable aligned NEON spilling by default.
Experiments show this to be a small speedup for modern ARM cores.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147689 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06 22:19:37 +00:00
Jakob Stoklund Olesen
59ecaae7b6 Abort AdjustBBOffsetsAfter early when possible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147685 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-06 21:40:15 +00:00
Jakob Stoklund Olesen
7255a4e133 Reapply r146997, "Heed spill slot alignment on ARM."
Now that canRealignStack() understands frozen reserved registers, it is
safe to use it for aligned spill instructions.

It will only return true if the registers reserved at the beginning of
register allocation allow for dynamic stack realignment.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147579 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05 00:26:57 +00:00
Jakob Stoklund Olesen
54f3b7a910 Avoid reserving an ARM base pointer during register allocation.
Once register allocation has started the reserved registers are frozen.

Fix the ARM canRealignStack() hook to respect the frozen register state.
Now the hook returns false if register allocation was started with frame
pointer elimination enabled.

It also returns false if register allocation started without a reserved
base pointer, and stack realignment would require a base pointer.  This
bug was breaking oggenc on armv6.

No test case, an upcoming patch will use this functionality to realign
the stack for spill slots when possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147578 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-05 00:26:52 +00:00
Evan Cheng
afad0fe59a Fix more places which should be checking for iOS, not darwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147513 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-04 01:55:04 +00:00
Jakob Stoklund Olesen
6d5b7cc235 Revert r146997, "Heed spill slot alignment on ARM."
This patch caused a miscompilation of oggenc because a frame pointer was
suddenly needed halfway through register allocation.

<rdar://problem/10625436>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147487 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 22:34:35 +00:00
Matt Beaumont-Gay
19055cc271 Fix malformed assert.
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147459 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-03 19:03:59 +00:00
Jakob Stoklund Olesen
43ea32ca04 Fix Comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147238 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-24 04:17:01 +00:00
Jakob Stoklund Olesen
f06f6f50e9 Experimental support for aligned NEON spills.
ARM targets with NEON units have access to aligned vector loads and
stores that are potentially faster than unaligned operations.

Add support for spilling the callee-saved NEON registers to an aligned
stack area using 16-byte aligned NEON loads and store.

This feature is off by default, controlled by an -align-neon-spills
command line option.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147211 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-23 00:36:18 +00:00
Bob Wilson
f4aea8f349 Add variants of the dispatchsetup pseudo for Thumb and !VFP. <rdar://10620138>
My change r146949 added register clobbers to the eh_sjlj_dispatchsetup pseudo
instruction, but on Thumb1 some of those registers cannot be used.  This
caused massive failures on the testsuite when compiling for Thumb1.  While
fixing that, I noticed that the eh_sjlj_setjmp instruction has a "nofp"
variant, and I realized that dispatchsetup needs the same thing, so I have
added that as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147204 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 23:39:48 +00:00
Jim Grosbach
4050bc4cab ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:19:05 +00:00
Bob Wilson
d2355e72c5 Add missing usesCustomInserter flag on Int_eh_sjlj_setjmp_nofp.
Noticed by inspection; I don't have a testcase for this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147188 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:12:44 +00:00
Jim Grosbach
21bcca81f4 Tidy up. Use predicate function a bit more liberally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147184 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:02:35 +00:00
Rafael Espindola
b975c27adc Fix incorrect relocation generation. Patch by Kristof Beyls.
Fixes PR11214.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 21:36:43 +00:00
Jim Grosbach
c7448f8d47 ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.

Partial for: rdar://10558523

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147170 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 19:55:21 +00:00
Jim Grosbach
8c748113eb Remove some bogus comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147169 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 19:45:01 +00:00
Jim Grosbach
1aa149f5ac ARM pre-UAL aliases. fcmp[sd].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147158 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 19:20:45 +00:00
Jim Grosbach
8d9550bde9 ARM assembler should accept shift-by-zero for any shifted-immediate operand.
Just treat it as-if the shift wasn't there at all. 'as' compatibility.

rdar://10604767

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 18:04:04 +00:00
Jim Grosbach
de626ad872 ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147152 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:37:00 +00:00
Jim Grosbach
18c8d12dea Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147151 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:17:10 +00:00
Jim Grosbach
f1a88fc474 Nuke invalid comment from copy/paste.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147150 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 17:04:50 +00:00
Rafael Espindola
6db2d92603 Make the virtual methods in ARMELFObjectWriter public.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147132 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 02:58:12 +00:00
Rafael Espindola
81fafde8a6 Hopefully fix the cmake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:11:01 +00:00
Rafael Espindola
7609785d2b Fix name in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147119 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:06:53 +00:00
Richard Smith
74cab51aa5 Unbreak cmake build after r147115.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147117 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 01:03:35 +00:00
Rafael Espindola
69bbda0391 Move the ARM specific parts of the ELF writer to Target/ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147115 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 00:37:50 +00:00
Jim Grosbach
f7c66fa0de ARM NEON mnemonic aliase for vrecpeq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147109 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:52:37 +00:00
Jim Grosbach
af33a0cfe0 ARM VFP optional data type on VMOV GPR<-->SPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:24:15 +00:00
Jim Grosbach
5f669fa8ba ARM NEON optional data type on VSWP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:09:28 +00:00
Jim Grosbach
4553fa3128 ARM NEON mnemonic aliases for vzipq and vswpq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:04:33 +00:00
Jim Grosbach
de4d83943a ARM asm parser should be more lenient w/ .thumb_func directive.
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.

rdar://10611140

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 22:30:16 +00:00
Jim Grosbach
520dc78d92 Thumb2 assembly parsing of 'mov rd, rn, rrx'.
Maps to the RRX instruction. Missed this case earlier.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 21:04:19 +00:00
Jim Grosbach
2cc5cda464 Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
These map to the ASR, LSR, LSL, ROR instruction definitions.

rdar://10615373

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:54:00 +00:00
Jakob Stoklund Olesen
a2a98fd0dd Move common code into an MRI function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:50:05 +00:00
Jim Grosbach
e6949b1399 ARM NEON assmebly parsing for VLD2 to all lanes instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:40:55 +00:00
Chad Rosier
8d0447c506 Fix a couple of copy-n-paste bugs. Noticed by George Russell!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 18:56:22 +00:00
Rafael Espindola
dc9a8a378d Reduce the exposure of Triple::OSType in the ELF object writer. This will
avoid including ADT/Triple.h in many places when the target specific bits are
moved.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 17:00:36 +00:00
Evan Cheng
1e33e8b715 Fix a couple of copy-n-paste bugs. Noticed by George Russell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 03:04:10 +00:00
Jim Grosbach
c931325d99 ARM assembly parsing allows constant expressions for lane indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 01:19:23 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:38:54 +00:00
Jim Grosbach
aee718beac ARM .req register name aliases are case insensitive, just like regnames.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:11:00 +00:00
Jim Grosbach
3cbe43fe69 Move comment to appropriate place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:26:38 +00:00
Jakob Stoklund Olesen
52346e964f Heed spill slot alignment on ARM.
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.

Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack.  Don't use aligned spill code in that case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:15:04 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 19:21:26 +00:00
Evan Cheng
afff941211 ARM target code clean up. Check for iOS, not Darwin where it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 18:26:50 +00:00
Jason W Kim
d7c9e08b6b First steps in ARM AsmParser support for .eabi_attribute and .arch
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146977 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 17:38:12 +00:00