it follows the order of the enum, not alphabetical.
The motivation is to make -mattr=+ssse3,+sse41
select SSE41 as it ought to. Added "ignored"
enum values of 0 to PPC and SPU to avoid compiler
warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47143 91177308-0d34-0410-b5e6-96231b3b80d8
on 64-bit builds. Analysis and original patch
by Török Edwin. Code audit found another place
with the same problem, also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45746 91177308-0d34-0410-b5e6-96231b3b80d8
emitted for external globals in PPC64-JIT-PIC mode (which is good because
we didn't handle them before!).
This also fixes a bug handling the picbase delta, which we would get wrong
in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32451 91177308-0d34-0410-b5e6-96231b3b80d8
support, and 64-bit register use are all consistent with each other.
Add a new "IsPPC" feature, to distinguish ppc32 vs ppc64 targets, use this
to configure TargetData differently. This not makes ppc64 blow up on lots
of stuff :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28825 91177308-0d34-0410-b5e6-96231b3b80d8
void foo(float a, int *b) { *b = a; }
to this:
_foo:
fctiwz f0, f1
stfiwx f0, 0, r4
blr
instead of this:
_foo:
fctiwz f0, f1
stfd f0, -8(r1)
lwz r2, -4(r1)
stw r2, 0(r4)
blr
This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26315 91177308-0d34-0410-b5e6-96231b3b80d8
// FIXME: revisit this when we have some kind of mechanism by which targets
// can decided legality of vector constants, of which there may be very
// many.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25733 91177308-0d34-0410-b5e6-96231b3b80d8
gcc -static produces on PPC. This is used for building kexts and other things.
With this, materializing the address of a global looks like:
lis r2, ha16(L_H$non_lazy_ptr)
la r3, lo16(L_H$non_lazy_ptr)(r2)
we're still emitting stubs for functions, which is wrong. That is next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24399 91177308-0d34-0410-b5e6-96231b3b80d8
option. Currently the only way to enable this is to specify the
64bitregs mattr flag. It is never enabled by default on any config yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23779 91177308-0d34-0410-b5e6-96231b3b80d8
'' is not a recognized processor for this target (ignoring processor)
Default to "generic" instead of "" for the default CPU.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23257 91177308-0d34-0410-b5e6-96231b3b80d8
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23192 91177308-0d34-0410-b5e6-96231b3b80d8
depending on the command line option. Now the command line option just
sets the subtarget as appropriate. G5 opts will now default to on on
G5-enabled nightly testers among other machines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22688 91177308-0d34-0410-b5e6-96231b3b80d8
