Commit Graph

83794 Commits

Author SHA1 Message Date
Kostya Serebryany
4f0c69623c [asan] more code to merge crash callbacks. Doesn't fully work yet, but allows to hold performance experiments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160361 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 11:04:12 +00:00
Nadav Rotem
5589a69f0a Fix a crash in the legalization of large vectors.
When truncating a result of a vector that is split we need
to use the result of the split vector, and not re-split the dead node.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160357 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 09:07:37 +00:00
Evan Cheng
f5c0539092 Implement r160312 as target indepedenet dag combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160354 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 08:31:11 +00:00
Simon Atanasyan
7072551feb Revert commit r160307. We decide to move builtins selection to the backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160352 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 08:14:45 +00:00
Evan Cheng
b4d4959fdd Make sure constant bitwidth is <= 64 bit before calling getSExtValue().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160350 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 07:47:50 +00:00
Evan Cheng
70e10d3fe4 This is another case where instcombine demanded bits optimization created
large immediates. Add dag combine logic to recover in case the large
immediates doesn't fit in cmp immediate operand field.

int foo(unsigned long l) {
  return (l>> 47) == 1;
}

we produce

  %shr.mask = and i64 %l, -140737488355328
  %cmp = icmp eq i64 %shr.mask, 140737488355328
  %conv = zext i1 %cmp to i32
  ret i32 %conv

which codegens to

movq    $0xffff800000000000,%rax
andq    %rdi,%rax
movq    $0x0000800000000000,%rcx
cmpq    %rcx,%rax
sete    %al
movzbl    %al,%eax
ret

TargetLowering::SimplifySetCC would transform
(X & -256) == 256 -> (X >> 8) == 1
if the immediate fails the isLegalICmpImmediate() test. For x86,
that's immediates which are not a signed 32-bit immediate.

Based on a patch by Eli Friedman.

PR10328
rdar://9758774


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160346 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 06:53:39 +00:00
Andrew Trick
06a27cc1aa Reapply r160340. LSR: Limit CollectSubexprs.
Speculatively fix crashes by code inspection. Can't reproduce them yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160344 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 05:30:37 +00:00
Andrew Trick
81ba5060ea Revert "LSR: try not to blow up solving combinatorial problems brute force."
Some units tests crashed on a different platform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160341 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 05:05:21 +00:00
Andrew Trick
6a51a7aea5 LSR: try not to blow up solving combinatorial problems brute force.
This places limits on CollectSubexprs to constrains the number of
reassociation possibilities. It limits the recursion depth and skips
over chains of nested recurrences outside the current loop.

Fixes PR13361. Although underlying SCEV behavior is still potentially bad.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160340 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 05:00:56 +00:00
Jim Grosbach
ac915b48d8 TableGen: Allow conditional instruction pattern in multiclass.
Define a 'null_frag' SDPatternOperator node, which if referenced in an
instruction Pattern, results in the pattern being collapsed to be as-if
'[]' had been specified instead. This allows supporting a multiclass
definition where some instaniations have ISel patterns associated and
others do not.

For example,
multiclass myMulti<RegisterClass rc, SDPatternOperator OpNode = null_frag> {
  def _x : myI<(outs rc:), (ins rc:), []>;
  def _r : myI<(outs rc:), (ins rc:), [(set rc:, (OpNode rc:))]>;
}

defm foo : myMulti<GRa, not>;
defm bar : myMulti<GRb>;

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160333 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-17 00:47:06 +00:00
Akira Hatanaka
1bda7863e3 Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160329 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 23:56:51 +00:00
Owen Anderson
b885dc8d39 Defer checking for registers in the MC AsmMatcher until the after user-defined match classes have been checked. This allows the creation of MatchClass's that are supersets of a register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160327 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 23:20:09 +00:00
Nuno Lopes
d49981a9bb fix PR13339 (remove the predecessor from the unwind BB when removing an invoke)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160325 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 22:49:40 +00:00
Nuno Lopes
7e733eab2f teach ConstantRange that zero times X is always zero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160317 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 20:47:16 +00:00
Evan Cheng
98819c9d1e For something like
uint32_t hi(uint64_t res)
{
        uint_32t hi = res >> 32;
        return !hi;
}

llvm IR looks like this:
define i32 @hi(i64 %res) nounwind uwtable ssp {
entry:
  %lnot = icmp ult i64 %res, 4294967296
  %lnot.ext = zext i1 %lnot to i32
  ret i32 %lnot.ext
}

The optimizer has optimize away the right shift and truncate but the resulting
constant is too large to fit in the 32-bit immediate field. The resulting x86
code is worse as a result:
        movabsq $4294967296, %rax       ## imm = 0x100000000
        cmpq    %rax, %rdi
        sbbl    %eax, %eax
        andl    $1, %eax

This patch teaches the x86 lowering code to handle ult against a large immediate
with trailing zeros. It will issue a right shift and a truncate followed by
a comparison against a shifted immediate.
        shrq    $32, %rdi
        testl   %edi, %edi
        sete    %al
        movzbl  %al, %eax

It also handles a ugt comparison against a large immediate with trailing bits
set. i.e. X >  0x0ffffffff -> (X >> 32) >= 1

rdar://11866926


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 19:35:43 +00:00
Nadav Rotem
c76fa8937d Minor cleanup and docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160311 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:56:39 +00:00
Simon Atanasyan
f6978ddbec MIPS: Create two definitions for __builtin_mips_shll_qb builtin.
The first variant accepts immediate number as the second argument.
The second variant accepts register operand as the second argument.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160307 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:51:39 +00:00
Nadav Rotem
7ee0e5ae60 Make ComputeDemandedBits return a deterministic result when computing an AssertZext value.
In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits
reported that some of the bits were both known to be one and known to be zero.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160305 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:34:53 +00:00
Tom Stellard
b1162b8d4b Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160303 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:53 +00:00
Tom Stellard
78a95d0986 Revert "include/llvm: Add R600 Intrinsics v6"
This reverts commit 600f7a90f3eef4c5108179b43e27cfd9e5de7cdc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160302 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:48 +00:00
Tom Stellard
38cda13c05 Revert "Build script changes for R600/SI Codegen v6"
This reverts commit e3013202259ed1e006c21817c63cf25d75982721.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160301 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:46 +00:00
Tom Stellard
a4be0720c5 Revert "test/CodeGen/R600: Add some basic tests v6"
This reverts commit 11d3457afcda7848448dd7f11b2ede6552ffb9ea.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160300 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:43 +00:00
Tom Stellard
d72304faf4 Revert "Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>"
This reverts commit 0258a6bdd30802f5cc0e8e57c8e768fde2aef590.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160299 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:41 +00:00
Tom Stellard
3685e223fd Revert "Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCommonTableGen."
This reverts commit ebc934ba32ee71abbb8f0f2eb6a0fbaa613ba0d2.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160298 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:40 +00:00
Tom Stellard
8e5471e4da Revert "Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional operator..."
This reverts commit 29f28bc14ad5a907f5dc849f004fafeec0aab33a.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160297 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:38 +00:00
Tom Stellard
80b9fe19c5 Revert "Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0)."
This reverts commit 4ba4acc1bc2561b944a571edbb6a2dc78e357dfe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160296 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:37 +00:00
Tom Stellard
82d6979f0a Revert "Target/AMDGPU: Fix includes, or msvc build failed."
This reverts commit fef4aa1b16fcf7a472559abbbcf4c1adc9eb5ca6.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160295 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:19:32 +00:00
Nuno Lopes
367308f798 make ConstantRange::getSetSize() properly compute the size of wrapped and full sets.
Make it always return APInts with the same bitwidth for the same ConstantRange bitwidth to simply clients

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160294 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 18:08:12 +00:00
Chad Rosier
3591955bce With r160248 in place this code is no longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160293 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 17:42:13 +00:00
Kostya Serebryany
2735cf4aa5 [asan] a bit more refactoring, addressed some of the style comments from chandlerc, partially implemented crash callback merging (under flag)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160290 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 17:12:07 +00:00
Aaron Ballman
09dab827b2 MSVC's implementation of isalnum will assert on characters > 255, so we need to use an unsigned char to ensure the integer promotion happens properly. This fixes an assert in debug builds with CodeGen\X86\utf8.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160286 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 16:18:18 +00:00
Kostya Serebryany
c0ed3e548c [asan] refactor instrumentation to allow merging the crash callbacks (not fully implemented yet, no functionality change except the BB order)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160284 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 16:15:40 +00:00
NAKAMURA Takumi
4a4d533fa7 Target/AMDGPU: Fix includes, or msvc build failed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160280 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 15:43:50 +00:00
NAKAMURA Takumi
b22d251dcc Target/AMDGPU/AMDILIntrinsicInfo.cpp: Use llvm_unreachable() in nonreturn function, instead of assert(0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160279 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 15:43:09 +00:00
NAKAMURA Takumi
addafc87a1 Target/AMDGPU/R600KernelParameters.cpp: Don't use "and", "or" as conditional operator...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160278 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 15:42:35 +00:00
Jack Carter
e035f65b16 Doubleword Shift Left Logical Plus 32
Mips shift instructions DSLL, DSRL and DSRA are transformed into
DSLL32, DSRL32 and DSRA32 respectively if the shift amount is between
32 and 63

Here is a description of DSLL:

Purpose: Doubleword Shift Left Logical Plus 32
To execute a left-shift of a doubleword by a fixed amount--32 to 63 bits

Description: GPR[rd] <- GPR[rt] << (sa+32)

The 64-bit doubleword contents of GPR rt are shifted left, inserting
 zeros into the emptied bits; the result is placed in
GPR rd. The bit-shift amount in the range 0 to 31 is specified by sa.

This patch implements the direct object output of these instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 15:14:51 +00:00
NAKAMURA Takumi
694fbf1777 Target/AMDGPU: [CMake] Fix dependencies. 1) Add intrinsics_gen. Add AMDGPUCommonTableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160276 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 15:09:11 +00:00
NAKAMURA Takumi
3f432a3888 Target/AMDGPU/R600KernelParameters.cpp: Fix two includes, <llvm/IRBuilder.h> and <llvm/TypeBuilder.h>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160275 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 15:08:47 +00:00
Alexey Samsonov
e0f5aedf97 Fix tests that failed on i686-win32 after r160248:
1. FileCheck-ize epilogue.ll and allow another asm instruction to restore %rsp.
2. Remove check in widen_arith-3.ll that was hitting instruction in epilogue instead of
vector add.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160274 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:33:36 +00:00
Tom Stellard
2015236dfc test/CodeGen/R600: Add some basic tests v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160273 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:17:19 +00:00
Tom Stellard
a93c8a89c1 Build script changes for R600/SI Codegen v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160272 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:17:16 +00:00
Tom Stellard
c3c661d4c1 include/llvm: Add R600 Intrinsics v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160271 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:17:14 +00:00
Tom Stellard
23dc769a9b AMDGPU: Add core backend files for R600/SI codegen v6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160270 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:17:08 +00:00
Kostya Serebryany
9db5b5ffa9 [asan] initialize asan error callbacks in runOnModule instead of doing that on-demand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160269 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 14:09:42 +00:00
Nadav Rotem
d93ea88cde Fix a bug in the 3-address conversion of LEA when one of the operands is an
undef virtual register. The problem is that ProcessImplicitDefs removes the
definition of the register and marks all uses as undef. If we lose the undef
marker then we get a register which has no def, is not marked as undef. The
live interval analysis does not collect information for these virtual
registers and we crash in later passes.

Together with Michael Kuperstein <michael.m.kuperstein@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160260 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 10:52:25 +00:00
Chandler Carruth
349f14c72c Revert r160254 temporarily.
It turns out that ASan relied on the at-the-end block insertion order to
(purely by happenstance) disable some LLVM optimizations, which in turn
start firing when the ordering is made more "normal". These
optimizations in turn merge many of the instrumentation reporting calls
which breaks the return address based error reporting in ASan.

We're looking at several different options for fixing this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160256 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 10:01:02 +00:00
Chandler Carruth
c3c8db9d25 Teach AddressSanitizer to create basic blocks in a more natural order.
This is particularly useful to the backend code generators which try to
process things in the incoming function order.

Also, cleanup some uses of IRBuilder to be a bit simpler and more clear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160254 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 08:58:53 +00:00
Chandler Carruth
2f58533d1e Add a basic test for AddressSanitizer. This is just a bare-bones
functionality test.

In general, unless the functionality is substantially separated, we
should lump more basic testing into this file. The test running
infrastructure likes having a few test files with more comprehensive
testing within them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160253 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 08:56:46 +00:00
Chandler Carruth
2994937203 Add support for attaching branch weight metadata directly from the IRBuilder.
Added a basic unit test for this with CreateCondBr. I didn't go all the
way and test the switch side as the boilerplate for setting up the
switch IRBuilder unit tests is a lot more. Fortunately, the two share
all the interesting code paths.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160251 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 07:45:06 +00:00
Chandler Carruth
4b31c4d93f Add a boring bit of boilerplate to start testing IRBuilder::CreateCondBr.
This is in anticipation of changing CreateCondBr and wanting to test
those changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160250 91177308-0d34-0410-b5e6-96231b3b80d8
2012-07-16 07:44:51 +00:00