Commit Graph

51287 Commits

Author SHA1 Message Date
Andrew Trick
4f3052403c Fix an overly general check in SimplifyIndvar to handle useless phi cycles.
The right way to check for a binary operation is
cast<BinaryOperator>. The original check: cast<Instruction> &&
numOperands() == 2 would match phi "instructions", leading to an
infinite loop in extreme corner case: a useless phi with operands
[self, constant] that prior optimization passes failed to remove,
being used in the loop by another useless phi, in turn being used by an
lshr or udiv.

Fixes PR11350: runaway iteration assertion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144935 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:36:35 +00:00
Kostya Serebryany
7cf2a04361 fall back to explicit list of allowed linkages when instrumenting globals in asan; add a test check that asan does not touch linkonce_odr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144933 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 23:14:59 +00:00
Chad Rosier
944d82ba06 Add TODO comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144920 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 21:46:13 +00:00
Craig Topper
d90a191685 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144896 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:49:38 +00:00
Chad Rosier
2fb82ce75d Dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144888 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:24:49 +00:00
Chad Rosier
478b06c980 When fast iseling a GEP, accumulate the offset rather than emitting a series of
ADDs.  MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD.  Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to 
coalesce ADDs.
rdar://10412592



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144886 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:15:58 +00:00
Craig Topper
ec43d1f553 Remove seemingly unnecessary duplicate VROUND definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144885 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 07:04:00 +00:00
Eli Friedman
9d434dbff3 Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
names for fwrite and fputs.

Fixes <rdar://problem/9815881>.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:27:36 +00:00
Chad Rosier
3bdb3c9b51 Don't unconditionally set the kill flag.
rdar://10456186


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144872 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 01:16:53 +00:00
Eli Friedman
d224c7879a Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144867 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-17 00:21:52 +00:00
Eli Friedman
4db4addcd4 Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144863 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 23:50:22 +00:00
Michael J. Spencer
11ba26db13 Object/COFF: Support common symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144861 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 23:36:12 +00:00
Jim Grosbach
2abba8496c Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:48:37 +00:00
Akira Hatanaka
620db8947a Lower 64-bit constant pool node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144849 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:44:38 +00:00
Akira Hatanaka
9b944a8da2 Lower 64-bit block address.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144847 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:42:10 +00:00
Jim Grosbach
b84acd2468 Fix encoding of NOP used for padding in ARM mode .align.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144842 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:40:25 +00:00
Akira Hatanaka
74c76347d3 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144841 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:39:56 +00:00
Akira Hatanaka
4fd40b3604 64-bit jump register instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144840 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:36:01 +00:00
Evan Cheng
2b89498979 Another missing X86ISD::MOVLPD pattern. rdar://10450317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144839 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 22:24:44 +00:00
Jim Grosbach
40a86ee20f ARM assembly parsing for shifted register operands for MOV instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144837 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:50:05 +00:00
Jim Grosbach
efed3d1f58 Clean up debug printing of ARM shifted operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144836 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:46:50 +00:00
Chad Rosier
053e69ad57 Add fast-isel stats to determine who's doing all the work, the
target-independent selector or the target-specific selector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144833 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:05:28 +00:00
Chad Rosier
f91488cc10 Fix the stats collection for fast-isel. The failed count was only accounting
for a single miss and not all predecessor instructions that get selected by
the selection DAG instruction selector.  This is still not exact (e.g., over
states misses when folded/dead instructions are present), but it is a step in
the right direction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144832 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 21:02:08 +00:00
Jim Grosbach
b598b04409 ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144814 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:12:24 +00:00
Jim Grosbach
48b368bcd5 ARM assembly parsing for RRX mnemonic.
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:05:59 +00:00
Pete Cooper
cd75e44173 Added missing comment about new custom lowering of DEC64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144811 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 19:03:23 +00:00
Evan Cheng
c3aa7c5c5a Disable expensive two-address optimizations at -O0. rdar://10453055
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144806 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:44:48 +00:00
Chad Rosier
508a1f4db1 Check to make sure we can select the instruction before trying to put the
operands into a register.  Otherwise, we may materialize dead code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:39:44 +00:00
Evan Cheng
14117c4477 Disable the assertion again. Looks like fastisel is still generating bad kill markers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144804 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:32:14 +00:00
Jim Grosbach
23f220705a ARM mode aliases for bitwise instructions w/ register operands.
rdar://9704684

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144803 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 18:31:45 +00:00
Bob Wilson
d0405aaabc Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144798 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 17:09:59 +00:00
NAKAMURA Takumi
5c283e98c9 lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144794 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 09:18:28 +00:00
Evan Cheng
b95fc31aa2 Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 08:38:26 +00:00
Bob Wilson
f1b41dd38d Record landing pads with a SmallSetVector to avoid multiple entries.
There may be many invokes that share one landing pad, and the previous code
would record the landing pad once for each invoke.  Besides the wasted
effort, a pair of volatile loads gets inserted every time the landing pad is
processed.  The rest of the code can get optimized away when a landing pad
is processed repeatedly, but the volatile loads remain, resulting in code like:

LBB35_18:
Ltmp483:
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r4, [r7, #-72]
        ldr     r2, [r7, #-68]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144787 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:57:21 +00:00
Craig Topper
12755b07ab Fix the execution domain on a bunch of SSE/AVX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144784 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:30:46 +00:00
Bob Wilson
20c918dfed Update the SP in the SjLj jmpbuf whenever it changes. <rdar://problem/10444602>
This same basic code was in the older version of the SjLj exception handling,
but it was removed in the recent revisions to that code.  It needs to be there.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144782 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:12:00 +00:00
Bob Wilson
eaab6ef6eb Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144781 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 07:11:57 +00:00
Craig Topper
2713d045e3 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144777 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 05:02:04 +00:00
Evan Cheng
0a405ae78a Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144776 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 04:55:01 +00:00
Nick Lewycky
ae10dd2859 Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when
looking at the size of the pointee. Fixes PR11390!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144773 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 03:49:48 +00:00
Evan Cheng
9bad88a9de If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144772 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 03:47:42 +00:00
Evan Cheng
2bee6a8bb7 RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144771 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 03:33:08 +00:00
Evan Cheng
ae7db7af44 Process all uses first before defs to accurately capture register liveness. rdar://10449480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144770 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 03:05:12 +00:00
Eli Friedman
d577df8e5a CONCAT_VECTORS can have more than two operands. PR11389.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144768 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 02:52:39 +00:00
Eli Friedman
b91b6001a6 Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144767 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 02:43:15 +00:00
Kostya Serebryany
800e03f598 AddressSanitizer, first commit (compiler module only)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144758 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 01:35:23 +00:00
Kostya Serebryany
a2a2d1fddd test commit to verify that commit access works (added blank line)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 01:14:38 +00:00
Owen Anderson
99aa14ff64 Rename MVT::untyped to MVT::Untyped to match similar nomenclature.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 01:02:57 +00:00
Andrew Trick
79f0bfcc20 Fix SCEV overly optimistic back edge taken count for multi-exit loops.
Fixes PR11375: Different results for 'clang++ huh.cpp'...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144746 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 00:52:40 +00:00
Chad Rosier
f56c60b571 Add FIXME comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144743 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-16 00:32:20 +00:00