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Author SHA1 Message Date
Eric Christopher
1e6d3ac709 This test is darwin only. Make it so(tm). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104418 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:55:55 +00:00
Bob Wilson
be751cfe9c Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by 
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104415 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:23:12 +00:00
Eric Christopher
8116ca5134 Add full bss data support for darwin tls variables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104414 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:10:22 +00:00
Devang Patel
65eb482e8f Collect variable information during endFunction() instead of beginFunction(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104412 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:04:14 +00:00
Eric Christopher
46099f14dc Add a new section and accessor for TLS data. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 00:00:58 +00:00
Bob Wilson
70fe6643d6 Clean up extra whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:53:55 +00:00
Eric Christopher
e81d010589 Make this LookAheadLimit, not the uninitialized LookAheadLeft. 
Evan please verify!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104408 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:40:03 +00:00
Chris Lattner
c2685a9c98 add a note 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104404 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:16:21 +00:00
Eric Christopher
070c1abbc9 Expand on comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:03:53 +00:00
Kevin Enderby
9d31d79493 Added retl for 32-bit x86 and added retq for 64-bit x86. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 23:01:38 +00:00
Eric Christopher
0df4a80e20 Fix comment and whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104392 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 22:39:11 +00:00
Chris Lattner
299f424f44 expand on the llvm ir bitcode dox. Patch by Peter Housel! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104391 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 22:20:54 +00:00
Evan Cheng
835810bbf8 Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104385 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:22:19 +00:00
Eric Christopher
9b00685bb6 Fix section attribute name. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104381 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:08:52 +00:00
Bob Wilson
78f006acdf Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 21:05:32 +00:00
Evan Cheng
1015ba7018 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104377 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
18b2c9d3bf Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction 
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104372 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 20:02:01 +00:00
Devang Patel
379fe83dda Simplify 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104338 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:49:09 +00:00
Dale Johannesen
acbf6348b1 Previous commit message should refer to 104308. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104337 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:44:47 +00:00
Dale Johannesen
e39859a838 Fix two bugs in 104348: 
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104336 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:40:15 +00:00
Nathan Jeffords
0783fb7e6d added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ZeroFillSize parameter 
If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104334 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:23:56 +00:00
Chris Lattner
a26a8471bd now that fp reg kill insertion stuff happens as a separate 
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104333 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:17:54 +00:00
Chris Lattner
d596c90030 Use less evil form of switch stmt. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104331 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:02:42 +00:00
Chris Lattner
d3d9ee1a4d use continue to reduce nesting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104330 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 18:01:24 +00:00
Chris Lattner
637e073181 pull a nested loop of this pass out to its own function, 
eliminating the gymnastics around the ContainsFPCode var.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104328 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:57:03 +00:00
Chris Lattner
6f569aabb5 modernize this pass a bit, fit in 80 columns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104326 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:49:07 +00:00
Chris Lattner
65569b8ddf constify accessor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104325 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
19f5f71bba Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." 
This reverts r104322. I think it was causing miscompilations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
00c53caa33 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple 
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:36:13 +00:00
Jakob Stoklund Olesen
63e6a488cb If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:32:16 +00:00
Matt Fleming
d8a33ddcfe Currently, createMachOStreamer() is invoked directly in llvm-mc which 
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 12:54:43 +00:00
Matt Fleming
7efaef6b82 Split out the x86_32 an x86_64 ELF backends as they handle ELF 
differently. This will make adding ELF support easier in the long run.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104317 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 11:39:07 +00:00
Matt Fleming
924c5e58f2 Add support for parsing the ELF .type assembler directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104316 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 11:36:59 +00:00
Lang Hames
24cdd2f82c Removed scaleNumbering method declaration from LiveInterval (not defined, not used). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 03:04:04 +00:00
Dale Johannesen
7d07b48b26 Fix i64->f64 conversion, x86-64, -no-sse. A bit 
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:52:33 +00:00
Evan Cheng
f7d87ee158 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:43:17 +00:00
Evan Cheng
b11ac950d6 Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:42:32 +00:00
Daniel Dunbar
596490682a Remove dead option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104303 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:27:55 +00:00
Devang Patel
c0c5a26dea Simplify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104302 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:10:20 +00:00
Daniel Dunbar
4ef6730632 Fix __crashreport_info__ declaration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 23:50:19 +00:00
Evan Cheng
1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 23:26:43 +00:00
Dan Gohman
0fe46d9b48 DominatorTree.getNode can return null for unreachable blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104290 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 22:46:54 +00:00
Dan Gohman
9f383eb950 Minor code cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104287 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 22:25:20 +00:00
Mikhail Glushenkov
dcc44670f4 Print a space after the colon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 21:11:37 +00:00
Dan Gohman
a552878508 Make Solve check its own post-condition, to reduce clutter in the 
top-level LSRInstance logic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:59:23 +00:00
Dan Gohman
76c315a26c Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:52:00 +00:00
Daniel Dunbar
4e7f8390c0 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:36:29 +00:00
Devang Patel
6ed0ce3240 Rename variable. add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:35:24 +00:00
Dan Gohman
402d43529c More code cleanups. Use iterators instead of indices when indices 
aren't needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104273 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:33:18 +00:00