Commit Graph

1142 Commits

Author SHA1 Message Date
Bill Wendling
393c4047c0 Improve the heuristic to emit the alias if the number of hard-coded registers
are also greater than the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-15 04:31:19 +00:00
Bill Wendling
740e5b3586 Heuristic: If the number of operands in the alias are more than the number of
operands in the aliasee, don't print the alias.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132963 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-14 03:17:20 +00:00
Roman Divacky
be234dabf4 Test that ".byte 1, 2, 3, 4" does the right thing.
Requested by nbjoerg!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132716 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-07 17:32:17 +00:00
Rafael Espindola
6536644713 Basic support for macros with explicit arguments.
We still don't handle

* default values
* :req
* :vararg
* \()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132656 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-05 02:43:45 +00:00
Nick Lewycky
e0b87032f5 Add support for @GOTPTOFF in i386 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132643 91177308-0d34-0410-b5e6-96231b3b80d8
2011-06-04 17:38:07 +00:00
Bruno Cardoso Lopes
895c1e2dee Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-31 03:33:27 +00:00
Rafael Espindola
04507f062f Use %rbp on a 64 bit test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132279 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-29 04:04:50 +00:00
Benjamin Kramer
06a8d54967 Move ARM specific test into the ARM subdir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132255 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-28 11:01:30 +00:00
Bruno Cardoso Lopes
be64b39431 ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 23:46:09 +00:00
Charles Davis
88c816453f Add the suffix to the Win64 EH data sections' names if given. Add a test for
this. XFAIL'd, because the COFF AsmParser can't handle .section yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132220 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 21:38:47 +00:00
Charles Davis
07cbe23173 Assorted fixes for Win64 EH unwind info emission:
- Flip order of bitfields. This gets our output matching GAS.
- Handle case where the end of the prolog wasn't specified.
- If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes.

Add a test for the latter two.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132188 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 15:10:25 +00:00
Charles Davis
3a5d7d0665 Add a test for Win64 EH unwind information emission.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132180 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-27 03:54:43 +00:00
Charles Davis
3ac7b034d6 Add a test for the chained directives that I forgot last time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132110 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 05:17:43 +00:00
Charles Davis
ca93138e11 Test .seh_startchained and .seh_endchained parsing.
Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.

The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132106 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-26 02:45:47 +00:00
Charles Davis
410ef2b263 Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with
them.

I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132084 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 21:43:45 +00:00
Charles Davis
575630ccb8 Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the
buggy methods that parse these directives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:51:25 +00:00
Charles Davis
47268164f3 Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and another
one I found by inspection).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132037 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 04:08:15 +00:00
Charles Davis
309213279e Add a test for the .seh_handler directive. Fix problems with the parsing
method exposed by the test. While we're at it, simplify the .seh_proc
parsing method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 01:33:42 +00:00
Bruno Cardoso Lopes
56926a3961 Fix PR9762
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-25 00:35:03 +00:00
Charles Davis
40de0e013a Test basic SEH directive-parsing functionality. Fix a latent bug exposed by
this test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-24 21:22:53 +00:00
Chris Lattner
d521d8bf92 add test from PR9164
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 22:35:34 +00:00
Chris Lattner
b8a21ad915 testcase for PR9378
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 22:32:53 +00:00
Johnny Chen
75f4296c7c Fix Bug 9386 - ARM disassembler failed to disassemble conditional bx
Modified the patch to .td file supplied by Jyun-Yan You.  Add a test case and
modified ARMDisassemblerCore.cpp a little bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 17:51:04 +00:00
Rafael Espindola
b8adb8af0f adds some attributes to attribute section when cpu is "xscale"
(this is what used in Android NDK, when architecture is ARMv5)

patch by Koan-Sin Tan

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:10:34 +00:00
Rafael Espindola
298c8e12ea fixes target address tBL and tBLX and sets relocation type
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)

Patch by koan-sin tan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-20 20:01:01 +00:00
Jason W Kim
861b9c6a39 This fixes one divergence between LLVM and binutils for ARM in the
text section.

Assume the following bit of annotated assembly:

.section	.data.rel.ro,"aw",%progbits
.align	2
.LAlpha:
.long	startval(GOTOFF)

.text
.align	2
.type	main,%function
.align	4

main: ;;; assume "main" starts at offset 0x20
0x0	push	{r11, lr}
0x4	movw	r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8	movt	r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc	... blah

.LBeta:
0x10	add	r0, pc, r0
0x14	... blah

.LGamma:
0x18	add	r1, pc, r1

Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions

00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha

And the encoded instructions in the .o file for main: must be

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec i.e. -20
28:	e34f0ff0 movt	r0, #65520	; 0xfff0 i.e. -16

However, llc (prior to this commit) generates the following sequence

00000020 <main>:
20:	e92d4800 push	{fp, lr}
24:	e30f0fec movw	r0, #65516	; 0xffec - i.e. -20
28:	e34f0fff movt	r0, #65535	; 0xffff - i.e. -1

What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.

This change agrees with what GNU as does, and makes the PIC code run.

MC/ARM/elf-movt.s covers this case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:55:25 +00:00
Rafael Espindola
a3bff99f0a ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.
Fixes PR9934.

We really need to start tblgening the relocation info :-(

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-19 20:32:34 +00:00
Johnny Chen
a96581f4f7 Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-18 20:32:41 +00:00
Rafael Espindola
6469540adf sets bit 0 of the function address of thumb function in .symtab
("T is 1 if the target symbol S has type STT_FUNC and the
symbol addresses a Thumb instruction ;it is 0 otherwise."
from "ELF for the ARM Architecture" 4.7.1.2)

Patch by Koan-Sin Tan!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-16 16:17:21 +00:00
Owen Anderson
18901d63bf Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-11 17:00:48 +00:00
Rafael Espindola
e3a0e987f3 On MachO, unlike ELF, there should be no relocation to produce the CIE pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131149 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 20:59:42 +00:00
Rafael Espindola
0d450dc659 In a debug_frame the cfi offset is to the start of the debug_frame section!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131129 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 15:20:23 +00:00
Rafael Espindola
40a7dbbeff Add support for producing .deubg_frame sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131121 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-10 03:54:12 +00:00
Jakob Stoklund Olesen
f695b3ad62 Explicitly request -join-physregs for some tests that depend on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130855 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 19:01:59 +00:00
Eric Christopher
b65122c873 Remove some random comments that snuck in from somewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130812 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-04 00:48:02 +00:00
Eric Christopher
2fc496fcf5 xmm0 is an implicit parameter in this and so shouldn't be in the
string template.

Fixes rdar://8493866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-03 01:28:32 +00:00
Daniel Dunbar
c8497b6a25 MCAsmLayout: Add support for computing the symbol offset of variables. Not
currently used, because variables don't get reported as being "defined".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130524 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 18:20:20 +00:00
Daniel Dunbar
90604ab725 MC: Change variable symbols to be recognized as defined, by assigning their sections based on FindAssociatedSection().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130523 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-29 18:20:17 +00:00
Johnny Chen
5a2336e794 Add tests for A8.6.110 NOP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130345 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-27 23:29:21 +00:00
Chandler Carruth
a4a2a03c31 Remove some hard coded CR-LFs. Some of these were the entire files, one of
these was just one line of a file. Explicitly set the eol-style property on the
files to try and ensure this fix stays.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130125 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-25 07:11:23 +00:00
Johnny Chen
597fa65373 Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) should
print out ldr, not ldr.n.

rdar://problem/9267772


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-22 19:12:43 +00:00
Rafael Espindola
1ac7fe0f4d Fix relative relocations. This is sufficient for running the rust testsuite with
MC :-)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129923 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-21 18:36:50 +00:00
Rafael Espindola
3660a847f1 Behave like gnu as when a relocation crosses sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129850 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-20 14:01:45 +00:00
Johnny Chen
3a96122c4a Thumb2 BFC was insufficiently encoded.
rdar://problem/9292717


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 22:52:15 +00:00
Johnny Chen
a704bc9354 A8.6.315 VLD3 (single 3-element structure to all lanes)
The a bit must be encoded as 0.

rdar://problem/9292625


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 22:49:08 +00:00
Joerg Sonnenberger
c25e8d8cea Add encoding tests for flds/filds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 19:25:31 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 05:18:47 +00:00
Johnny Chen
de29a52940 The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions
(single element or n-element structure to all lanes).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-15 00:10:45 +00:00
Johnny Chen
cd695fdac1 Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 19:13:28 +00:00
Bill Wendling
d336de318e As Dan pointed out, movzbl, movsbl, and friends are nicer than their alias
(movzx/movsx) because they give more information. Revert that part of the patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:46:37 +00:00