Commit Graph

9 Commits

Author SHA1 Message Date
Eric Christopher
10b963632c Reuse a bunch of cached subtargets and remove getSubtarget calls
without a Function argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227647 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-31 00:06:45 +00:00
Richard Sandiford
4c925c60eb [SystemZ] Use interlocked-access 1 instructions for CodeGen
...namely LOAD AND ADD, LOAD AND AND, LOAD AND OR and LOAD AND EXCLUSIVE OR.
LOAD AND ADD LOGICAL isn't really separately useful for LLVM.

I'll look at adding reusing the CC results in new year.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197985 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24 15:18:04 +00:00
Richard Sandiford
f7e24324ba [SystemZ] Add MC support for interlocked-access 1 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-24 15:14:05 +00:00
Richard Sandiford
086791eca2 Add TargetLowering::prepareVolatileOrAtomicLoad
One unusual feature of the z architecture is that the result of a
previous load can be reused indefinitely for subsequent loads, even if
a cache-coherent store to that location is performed by another CPU.
A special serializing instruction must be used if you want to force
a load to be reattempted.

Since volatile loads are not supposed to be omitted in this way,
we should insert a serializing instruction before each such load.
The same goes for atomic loads.

The patch implements this at the IR->DAG boundary, in a similar way
to atomic fences.  It is a no-op for targets other than SystemZ.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196905 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10 10:36:34 +00:00
Richard Sandiford
793ce99ea7 [SystemZ] Automatically detect zEC12 and z196 hosts
As on other hosts, the CPU identification instruction is priveleged,
so we need to look through /proc/cpuinfo.  I copied the PowerPC way of
handling "generic".

Several tests were implicitly assuming z10 and so failed on z196.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193742 91177308-0d34-0410-b5e6-96231b3b80d8
2013-10-31 12:14:17 +00:00
Richard Sandiford
d954716e75 [SystemZ] Add FI[EDX]BRA
These are extensions of the existing FI[EDX]BR instructions, but use a spare
bit to suppress inexact conditions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188894 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-21 08:58:08 +00:00
Richard Sandiford
f3068d02e5 [SystemZ] Add RISBLG and RISBHG instruction definitions
The next patch will make use of RISBLG for codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187490 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-31 11:17:35 +00:00
Richard Sandiford
b284e1bf08 [SystemZ] Add STOC and STOCG
These instructions are allowed to trap even if the condition is false,
so for now they are only used for "*ptr = (cond ? x : *ptr)"-style
constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187111 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-25 08:57:02 +00:00
Richard Sandiford
eddfaad1ef [SystemZ] Start adding z196 and zEC12 support
This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.

insn-bad.s tests that some form of error is reported when using these
instructions on z10.  More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:09:03 +00:00