Commit Graph

91904 Commits

Author SHA1 Message Date
Duncan Sands
5d042c6374 Fix formatting. Patch by o11c.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181189 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 08:55:45 +00:00
Michael Kuperstein
2720248ae5 Fix slightly too aggressive conact_vector optimization.
(Would sometimes optimize away conacts used to extend a vector with undef values)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181186 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 08:06:13 +00:00
Bill Wendling
10c6d2c84c Add a testcase that checks that we generate functions with frame
pointers or not depending upon the function attributes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181180 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 05:45:57 +00:00
Rafael Espindola
cf896576c8 XFAIL for cygwin.
Looks like symbol resolution is not working on cygwin, the test fails
because __gxx_personality_v0 is not found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 03:35:56 +00:00
Nadav Rotem
37d38b7668 Update the comment to mention that we use TTI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181178 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 03:06:36 +00:00
Nadav Rotem
4ee312bac1 Revert r164763 because it introduces new shuffles.
Thanks Nick Lewycky for pointing this out.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181177 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 02:39:09 +00:00
Matt Arsenault
8b9dc21d6f Fix unchecked uses of DominatorTree in MemoryDependenceAnalysis.
Use unknown results for places where it would be needed

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 02:07:24 +00:00
Rafael Espindola
eaf14786ca Fix const merging when an alias of a const is llvm.used.
We used to disable constant merging not only if a constant is llvm.used, but
also if an alias of a constant is llvm.used. This change fixes that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 01:48:55 +00:00
Rafael Espindola
f93b6d2ec5 This should also fail on ARM.
We currently have no way to register new eh frames on ARM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181172 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 22:42:34 +00:00
Rafael Espindola
9caaa902c3 Fix XFAIL line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181171 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 21:30:10 +00:00
Rafael Espindola
b9e20bae2e XFAIL this on ppc64.
It looks like eh uses an unimplemented relocation on pp64

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181169 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 21:04:18 +00:00
Rafael Espindola
c8b9551a8f Port ExceptionDemo to MCJIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181168 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 20:57:58 +00:00
Rafael Espindola
a2e40fbd62 Add EH support to the MCJIT.
This gets exception handling working on ELF and Macho (x86-64 at least).
Other than the EH frame registration, this patch also implements support
for GOT relocations which are used to locate the personality function on
MachO.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181167 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 20:43:10 +00:00
Evan Cheng
9f2bebbc28 Test case for r181160 and r181161. rdar://13782395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181162 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 18:07:15 +00:00
Evan Cheng
0553e1efcd ARM AnalyzeBranch should conservatively return true when it sees a predicated
indirect branch at the end of the BB. Otherwise if-converter, branch folding
pass may incorrectly update its successor info if it consider BB as fallthrough
to the next BB.

rdar://13782395


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181161 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 18:06:32 +00:00
Evan Cheng
9a28cc14a9 Teach if-converter to avoid removing BBs whose addresses are takne. rdar://13782395
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181160 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 18:03:49 +00:00
Benjamin Kramer
acc47c738d LoopVectorize: Print values instead of pointers in debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181157 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 14:54:52 +00:00
Richard Osborne
e0c3454771 [docs] Update Target Feature Matrix for the XCore backend.
Disassembler support has recently been added. Fill in some other unknowns
at the same time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181156 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 14:09:55 +00:00
Richard Osborne
589ddc9887 [XCore] Add LDAPB instructions.
With the change the disassembler now supports the XCore ISA in its
entirety.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 13:36:53 +00:00
Richard Osborne
fae63389d9 [XCore] Update LDAP to use pcrel_imm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181154 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 13:33:10 +00:00
Richard Osborne
24aeab3d8a [XCore] Rename calltarget -> pcrel_imm.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181153 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 13:29:02 +00:00
Richard Osborne
c601bd69d5 [XCore] Add BLRB instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 13:24:16 +00:00
Richard Osborne
1114b0ec15 [XCore] Remove '-' from back branch asm syntax.
Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 13:20:22 +00:00
Benjamin Kramer
e210df20d3 InlineSpiller: Remove quadratic behavior.
No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181149 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 11:29:14 +00:00
Stepan Dyatkovskiy
46abfcf418 For ARM backend, fixed "byval" attribute support.
Now even the small structures could be passed within byval (small enough
to be stored in GPRs).
In regression tests next function prototypes are checked:

PR15293:
  %artz = type { i32 }
  define void @foo(%artz* byval %s)
  define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2)
foo: "s" stored in R0
foo2: "s" stored in R0, "s2" stored in R2.

Next AAPCS rules are checked:
5.5 Parameters Passing, C.4 and C.5,
"ParamSize" is parameter size in 32bit words:
-- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4.
   Parameter should be sent to the stack; NCRN := R4.
-- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4.
   Parameter stored in GPRs; NCRN += ParamSize.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 07:48:36 +00:00
Arnold Schwaighofer
46e7e6f39e Add missing PatternMatch.cpp to CMakeLists.txt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 02:14:28 +00:00
Arnold Schwaighofer
f127be1e38 PatternMatch: Fix documentation - 'function' not 'attribute'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181146 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 02:01:41 +00:00
David Majnemer
526f3ed7da Remove a recently redundant transform from X86ISelLowering.
X86ISelLowering has support to treat:
(icmp ne (and (xor %flags, -1), (shl 1, flag)), 0)

as if it were actually:
(icmp eq (and %flags, (shl 1, flag)), 0)

However, r179386 has code at the InstCombine level to handle this.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 02:00:10 +00:00
Arnold Schwaighofer
87defd0924 LoopVectorize: Add support for floating point min/max reductions
Add support for min/max reductions when "no-nans-float-math" is enabled. This
allows us to assume we have ordered floating point math and treat ordered and
unordered predicates equally.

radar://13723044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 01:54:48 +00:00
Arnold Schwaighofer
e79d92c592 PatternMatch: Matcher for (un)ordered floating point min/max
Add support for matching 'ordered' and 'unordered' floating point min/max
constructs.

In LLVM we can express min/max functions as a combination of compare and select.
We have support for matching such constructs for integers but not for floating
point. In floating point math there is no total order because of the presence of
'NaN'. Therefore, we have to be careful to preserve the original fcmp semantics
when interpreting floating point compare select combinations as a minimum or
maximum function. The resulting 'ordered/unordered' floating point maximum
function has to select the same value as the select/fcmp combination it is based
on.

 ordered_max(x,y)   = max(x,y) iff x and y are not NaN, y otherwise
 unordered_max(x,y) = max(x,y) iff x and y are not NaN, x otherwise
 ordered_min(x,y)   = min(x,y) iff x and y are not NaN, y otherwise
 unordered_min(x,y) = min(x,y) iff x and y are not NaN, x otherwise

This matches the behavior of the underlying select(fcmp(olt/ult/.., L, R), L, R)
construct.

Any code using this predicate has to preserve this semantics.

A follow-up patch will use this to implement floating point min/max reductions
in the vectorizer.

radar://13723044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 01:54:46 +00:00
Arnold Schwaighofer
f852472823 LoopVectorizer: Cleanup of miminimum/maximum pattern match code
No need for setting the operands. The pointers are going to be bound by the
matcher.

radar://13723044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181142 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 01:54:44 +00:00
Arnold Schwaighofer
c1738fdadd LoopVectorize: We don't need an identity element for min/max reductions
We can just use the initial element that feeds the reduction.

  max(max(x, y), z) == max(max(x,y), max(x,z))

radar://13723044

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181141 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 01:54:42 +00:00
Dmitri Gribenko
5c332dbd30 Add ArrayRef constructor from None, and do the cleanups that this constructor enables
Patch by Robert Wilhelm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-05 00:40:33 +00:00
Nadav Rotem
76be9bf67e whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 23:27:32 +00:00
Nadav Rotem
0fb6523eae Fix an odd comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 23:24:56 +00:00
Tim Northover
7428539a1c AArch64: enable MCJIT and tests now that everything passes.
This removes dire warnings about AArch64 being unsupported and enables
the tests when appropriate on this platform.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181135 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:14:22 +00:00
Tim Northover
d52eaae157 AArch64: implement 64-bit absolute relocation in MCJIT
This is about the simplest relocation, but surprisingly rare in actual
code.

It occurs in (for example) the MCJIT test test-ptr-reloc.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181134 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:14:14 +00:00
Tim Northover
4a9b6b798d AArch64: add stubs to support long function calls on MCJIT
As with global accesses, external functions could exist anywhere in
memory. Therefore the stub must create a complete 64-bit address. This
patch implements the fragment as (roughly):
    movz x16, #:abs_g3:somefunc
    movk x16, #:abs_g2_nc:somefunc
    movk x16, #:abs_g1_nc:somefunc
    movk x16, #:abs_g0_nc:somefunc
    br x16

In principle we could save 4 bytes by using a literal-load instead,
but it is unclear that would be more efficient and can only be tested
when real hardware is readily available.

This allows (for example) the MCJIT test 2003-05-07-ArgumentTest to
pass on AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181133 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:14:09 +00:00
Tim Northover
654c2d6b7a AArch64: implement relocations for global access
The large memory model (default and main viable for JIT) emits
addresses in need of relocation as
    movz x0, #:abs_g3:somewhere
    movk x0, #:abs_g2_nc:somewhere
    movk x0, #:abs_g1_nc:somewhere
    movk x0, #:abs_g0_nc:somewhere

To support this we must implement those four relocations in the
dynamic loader.

This allows (for example) the test-global.ll MCJIT test to pass on
AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181132 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:14:04 +00:00
Tim Northover
85829bb98a AArch64: implement first relocation required for MCJIT
R_AARCH64_PCREL32 is present in even trivial .eh_frame sections and so
is required to compile any function without the "nounwind" attribute.

This change implements very basic infrastructure in the RuntimeDyldELF
file and allows (for example) the test-shift.ll MCJIT test to pass
on AArch64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:13:59 +00:00
Tim Northover
bd121f5b3a Build system changes to enable MCJIT on AArch64
These changes just allow AArch64 to take part in the MCJIT world when
built correctly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 20:13:52 +00:00
Tim Northover
9a29cf281e AArch64: use __clear_cache under GCCish environments
AArch64 is going to need some kind of cache-invalidation in order to
successfully JIT since it has a weak memory-model. This is provided by
a __clear_cache builtin in libgcc, which acts very much like the
32-bit ARM equivalent (on platforms where it exists).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181129 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 18:52:44 +00:00
Richard Osborne
7153a30610 Fix buildbot failure on 64 bit linux due to std::max() having different
operand types.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181128 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:41:01 +00:00
Richard Osborne
43c7abee14 [XCore] Remove unused operand type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181127 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:30:05 +00:00
Richard Osborne
6ffbf6ea8f [XCore] Make use of the target independent global address offset folding.
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:24:33 +00:00
Richard Osborne
40827bc716 [XCore] Simplify code that checks for an aligned base plus a constant.
The code now makes use of ComputeMaskedBits,
SelectionDAG::isBaseWithConstantOffset and TargetLowering::isGAPlusOffset
where appropriate reducing the amount of logic needed in XCoreISelLowering.
No intended functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181125 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:17:10 +00:00
Richard Osborne
597432fbe5 [XCore] Move lowering of thread local storage to a separate pass.
Thread local storage is not supported by the XMOS linker so we handle
thread local variables by lowering the variable to an array of n elements
(where n is the number of hardware threads per core, currently 8
for all XMOS devices) indexed by the the current thread ID.

Previously this lowering was spread across the XCoreISelLowering and the
XCoreAsmPrinter classes. Moving this to a separate pass should be much
cleaner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181124 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 17:01:55 +00:00
Tim Northover
effc16bb49 AArch64: assert code model is small for TLS accesses
Supporting TLS in the large memory model is rather difficult at the
moment, so make sure no-one gets into difficulties by mistake.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181121 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:11 +00:00
Tim Northover
79c1c092df AArch64: support literal pool access in large memory model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181120 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:07 +00:00
Tim Northover
cd1b09b25b AArch64: support large code model for jump-tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181119 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-04 16:54:00 +00:00