Jim Grosbach
5f669fa8ba
ARM NEON optional data type on VSWP instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:09:28 +00:00
Jim Grosbach
4553fa3128
ARM NEON mnemonic aliases for vzipq and vswpq.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:04:33 +00:00
Jakub Staszak
d4895ded27
Revert patch from 147090. There is not point to make code less readable if we
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don't get any serious benefit there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147101 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:02:08 +00:00
Jim Grosbach
de4d83943a
ARM asm parser should be more lenient w/ .thumb_func directive.
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Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147100 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 22:30:16 +00:00
Dan Gohman
483716015f
Fix a copy+pasto. No testcase, because the symptoms of dereferencing
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an invalid iterator aren't reproducible. rdar://10614085.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147098 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 21:43:50 +00:00
Jim Grosbach
520dc78d92
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
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Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 21:04:19 +00:00
Chad Rosier
5c0d761d63
Fix 80-column violations.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147095 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:59:09 +00:00
Jim Grosbach
2cc5cda464
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
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These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:54:00 +00:00
Nick Lewycky
6c6fcc4610
Continue counting intrinsics as instructions (except when they aren't, such as
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debug info) and for being vector operations. Fixes regression from r147037.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147093 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:26:03 +00:00
Nick Lewycky
144bef462b
Fix typo and spacing, no functionality change.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147092 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:21:55 +00:00
Jakub Staszak
73db975498
- Change a few operator[] to lookup which is cheaper.
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- Add some constantness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147090 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:18:54 +00:00
Lang Hames
b638c789be
Oops - LiveIntervalUnion.cpp file does use std::find. Moving STL header include to LiveIntervalUnion.cpp file.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147089 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:16:11 +00:00
Lang Hames
bac22fac7d
Remove disused STL header include.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147088 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:12:54 +00:00
Rafael Espindola
e8526d030f
Switch from WriteEFlags to getEFlags in preparation for moving it
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to Target/.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147087 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 20:09:46 +00:00
Jakob Stoklund Olesen
a2a98fd0dd
Move common code into an MRI function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147071 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:50:05 +00:00
Jim Grosbach
e6949b1399
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:40:55 +00:00
Chad Rosier
649326ab15
No case stmt for BUILD_VECTOR in PerformDAGCombine(), so I assume this isn't
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necessary. Please chime in if I'm mistaken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147065 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 19:14:52 +00:00
Chad Rosier
8d0447c506
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147064 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 18:56:22 +00:00
Manuel Klimek
84cbb6f00d
Changes the JSON parser to use the SourceMgr.
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Diagnostics are now emitted via the SourceMgr and we use MemoryBuffer
for buffer management. Switched the code to make use of the trailing
'0' that MemoryBuffer guarantees where it makes sense.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147063 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 18:16:39 +00:00
Rafael Espindola
edae8e1e4d
Move the X86 specific bits of the ELF writer to the Target/X86 directory.
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Other targets will follow shortly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147060 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 17:30:17 +00:00
Rafael Espindola
dc9a8a378d
Reduce the exposure of Triple::OSType in the ELF object writer. This will
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avoid including ADT/Triple.h in many places when the target specific bits are
moved.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147059 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 17:00:36 +00:00
Rafael Espindola
c677e790e5
Small refactoring so that RelocNeedsGOT can stay in the target independent
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side when the target specific bits are moved to the Target directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147053 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 14:26:29 +00:00
Manuel Klimek
9a31fb0c38
Removes unused field TheError from LLLexer.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147049 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 10:02:45 +00:00
Craig Topper
224c1b275d
Remove mode specific disassembler classes and just call X86GenericDisassembler constructor with appropriate argument in the creation functions. This removes a few tables that needed to be anchored.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 08:06:52 +00:00
Craig Topper
e1a18a66df
Fix typo in a couple comments
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147045 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 06:30:53 +00:00
Nick Lewycky
20aded5912
A call to a function marked 'noinline' is not an inline candidate. The sole
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call site of an intrinsic is also not an inline candidate. While here, make it
more obvious that this code ignores all intrinsics. Noticed by inspection!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147037 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 06:06:30 +00:00
Nick Lewycky
8369687576
Make some intrinsics safe to speculatively execute.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147036 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 05:52:02 +00:00
Evan Cheng
1e33e8b715
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147032 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 03:04:10 +00:00
Jim Grosbach
c931325d99
ARM assembly parsing allows constant expressions for lane indices.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147028 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 01:19:23 +00:00
Jim Grosbach
3471d4fbbd
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:38:54 +00:00
Akira Hatanaka
c7541c49a9
Fix bug in zero-store peephole pattern reported in pr11615.
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The patch and test case were originally written by Mans Rullgard.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147024 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:31:10 +00:00
Akira Hatanaka
c79507a4dd
Expand 64-bit CTLZ nodes if target architecture does not support it. Add test
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case for DCLO and DCLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147022 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:20:27 +00:00
Akira Hatanaka
7f162743fc
Expand 64-bit CTPOP and CTTZ.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147021 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:14:05 +00:00
Akira Hatanaka
9aed504c82
Expand 64-bit atomic load and store.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147019 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 00:02:58 +00:00
Akira Hatanaka
c0ea04389c
Add definition of DSBH (Double Swap Bytes within Halfwords) and
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DSHD (Double Swap Halfwords within Doublewords). Add a pattern which replaces
64-bit bswap with a DSBH and DSHD pair.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147017 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:56:43 +00:00
Akira Hatanaka
4d2b0f3ce7
Add definition of WSBH (Word Swap Bytes within Halfwords), which is an
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instruction supported by mips32r2, and add a pattern which replaces bswap with
a ROTR and WSBH pair.
WSBW is removed since it is not an instruction the current architectures
support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147015 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:47:44 +00:00
Akira Hatanaka
e1bcd6b5c6
64-bit uint-fp conversion nodes are expanded.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147014 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:40:56 +00:00
Akira Hatanaka
9388383b34
Enable custom lowering DYNAMIC_STACKALLOC nodes.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147013 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:35:46 +00:00
Akira Hatanaka
056a1bc40f
Set the correct stack pointer register that should be saved or restored.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147012 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:28:36 +00:00
Chris Lattner
1a31f3b90c
Fix a nasty bug in the type remapping stuff that I added that is breaking kc++ on
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the build bot in some cases. The basic issue happens when a source module contains
both a "%foo" type and a "%foo.42" type. It will see the later one, check to see if
the destination module contains a "%foo" type, and it will return true... because
both the source and destination modules are in the same LLVMContext. We don't want
to map source types to other source types, so don't do the remapping if the mapped
type came from the source module.
Unfortunately, I've been unable to reduce a decent testcase for this, kc++ is
pretty great that way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147010 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:14:57 +00:00
Jim Grosbach
aee718beac
ARM .req register name aliases are case insensitive, just like regnames.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147009 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:11:00 +00:00
Akira Hatanaka
2fd0475cdb
Add function MipsDAGToDAGISel::SelectMULT and factor out code that generates
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nodes needed for multiplication. Add code for selecting 64-bit MULHS and MULHU
nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147008 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 23:10:57 +00:00
Akira Hatanaka
49d534bb3d
Fix indentation.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147007 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:58:01 +00:00
Akira Hatanaka
8dc684d2a2
64-bit data directive.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147005 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:52:19 +00:00
Akira Hatanaka
ef43c2de86
32-to-64-bit sext_inreg pattern.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147004 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:40:40 +00:00
Akira Hatanaka
acb5a06f7a
Add 64-bit extload patterns.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147003 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:36:08 +00:00
Akira Hatanaka
ab05b6c227
Add patterns for matching extloads with 64-bit address. The patterns are enabled
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only when the target ABI is N64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147001 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:33:53 +00:00
Jim Grosbach
3cbe43fe69
Move comment to appropriate place.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147000 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:26:38 +00:00
Akira Hatanaka
990d639f55
Add code in MipsDAGToDAGISel for selecting constant +0.0.
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MIPS64 can generate constant +0.0 with a single DMTC1 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:25:50 +00:00
Jakob Stoklund Olesen
52346e964f
Heed spill slot alignment on ARM.
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Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146997 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 22:15:04 +00:00