3 Commits

Author	SHA1	Message	Date
Kevin Enderby	f49a4092bc	Fix the encoding of the armv7m (MClass) for MSR registers other than aspr, ... iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8	2012-06-15 22:14:44 +00:00
Kevin Enderby	0fd4f3c8de	Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing ... the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8	2012-05-17 22:18:01 +00:00
James Molloy	acad68da50	Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. ... Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8	2011-09-28 14:21:38 +00:00