Jack Carter
b8145e3881
Mips assembler: Explicit floating point condition register recognition.
...
This patch allows the assembler to recognize $fcc0
as a valid register for conditional move instructions.
Corresponding test cases have been added.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-15 22:21:55 +00:00
Nico Rieck
ef1762b6a1
Use object file specific section type for initial text section
...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-14 21:18:36 +00:00
Jack Carter
de33227462
Adding support for instructions mfc0, mfc2, mtc0, mtc2
...
move from and to coprocessors 0 and 2.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-06 01:17:37 +00:00
Jack Carter
f740d6e328
The Mips standalone assembler fpu instruction support.
...
Test cases included
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 00:23:42 +00:00
