Chris Lattner
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65303d6bd7
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Teach tblgen about instruction operands that have multiple MachineInstr
operands, digging into them to find register values (used on X86). Patch
by Evan Cheng!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-11-19 07:05:57 +00:00 |
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Chris Lattner
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5f89bf0f9d
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spell this variable right
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23095 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-08-26 20:42:52 +00:00 |
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Chris Lattner
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8b50f9b8dc
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Expose a new flag to TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23094 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-08-26 20:40:46 +00:00 |
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Chris Lattner
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0e384b66a7
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For now, just emit empty operand info structures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22910 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-08-19 16:57:28 +00:00 |
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Chris Lattner
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cfbf96aa9c
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Figure out how many operands each instruction has, keep track of whether
or not it's variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22885 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-08-18 23:38:41 +00:00 |
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Misha Brukman
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3da94aec4d
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Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21428 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-04-22 00:00:37 +00:00 |
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Chris Lattner
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aad75aa1a2
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Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19243 91177308-0d34-0410-b5e6-96231b3b80d8
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2005-01-02 02:29:04 +00:00 |
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Nate Begeman
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cdd66b524f
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Add support for the isLoad and isStore flags, needed by the instruction scheduler
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16554 91177308-0d34-0410-b5e6-96231b3b80d8
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2004-09-28 21:01:45 +00:00 |
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Chris Lattner
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5b71d3af35
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Turn the hasDelaySlot flag into the M_DELAY_SLOT_FLAG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16553 91177308-0d34-0410-b5e6-96231b3b80d8
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2004-09-28 18:38:01 +00:00 |
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Chris Lattner
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175580c0f3
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Make the AsmWriter a first-class tblgen object. Allow targets to specify
name of the generated asmwriter class, and the name of the format string.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15747 91177308-0d34-0410-b5e6-96231b3b80d8
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2004-08-14 22:50:53 +00:00 |
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Chris Lattner
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cf03da0ce9
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Start parsing more information from the Operand information
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15644 91177308-0d34-0410-b5e6-96231b3b80d8
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2004-08-11 02:22:39 +00:00 |
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Chris Lattner
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87c5905e0b
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Parse the operand list of the instruction. We currently support register and immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15390 91177308-0d34-0410-b5e6-96231b3b80d8
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2004-08-01 07:42:39 +00:00 |
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Chris Lattner
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ec3524064c
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Add, and start using, the CodeGenInstruction class. This class represents
an instance of the Instruction tablegen class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15385 91177308-0d34-0410-b5e6-96231b3b80d8
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2004-08-01 05:04:00 +00:00 |
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