Commit Graph

92627 Commits

Author SHA1 Message Date
Rafael Espindola
6afb65c2b7 Revert "R600: Add a pass that merge Vector Register"
This reverts commit r183279. CodeGen/R600/texture-input-merge.ll was failing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183286 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:48:30 +00:00
Rafael Espindola
6c1202c459 Handle relocations that don't point to symbols.
In ELF (as in MachO), not all relocations point to symbols. Represent this
properly by using a symbol_iterator instead of a SymbolRef. Update llvm-readobj
ELF's dumper to handle relocatios without symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-05 01:33:53 +00:00
Sean Silva
cc5a6cb0a2 [docs] Replace non-existent LLVM_YAML_UNIQUE_TYPE() macro
LLVM_YAML_STRONG_TYPEDEF() is the correct macro to perform this function.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183280 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:36:41 +00:00
Vincent Lejeune
bbbdba891b R600: Add a pass that merge Vector Register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183279 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:26 +00:00
Vincent Lejeune
e67a4afb5d R600: Const/Neg/Abs can be folded to dot4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183278 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 23:17:15 +00:00
Evan Cheng
00ed010d9e Cortex-R5 can issue Thumb2 integer division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183275 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:52:09 +00:00
Arnold Schwaighofer
8a227084a5 Revert series of sched model patches until I figure out what is going on.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183273 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:35:17 +00:00
Arnold Schwaighofer
f500aa0b24 ARM sched model: Add VFP div instruction on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:16:08 +00:00
Arnold Schwaighofer
858f6f8899 ARM sched model: Add SIMD/VFP load/store instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183270 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:16:07 +00:00
Arnold Schwaighofer
e52041c16e ARM sched model: Add integer VFP/SIMD instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183269 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:16:05 +00:00
Arnold Schwaighofer
f3a2329d33 ARM sched model: Add integer load/store instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183268 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:16:04 +00:00
Arnold Schwaighofer
755d1295a5 ARM sched model: Add integer arithmetic instructions on Swift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:16:02 +00:00
Arnold Schwaighofer
eb9948e781 ARM sched model: Cortex A9 - More InstRW sched resources
Add more InstRW mappings.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183266 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:16:00 +00:00
Arnold Schwaighofer
002faf20a7 ARM sched model: Add branch thumb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183265 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:59 +00:00
Arnold Schwaighofer
16d915018b ARM sched model: Add branch thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:57 +00:00
Arnold Schwaighofer
36ea791280 ARM sched model: Add branch instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:56 +00:00
Arnold Schwaighofer
fdbca2faac ARM sched model: Add preload thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:54 +00:00
Arnold Schwaighofer
d3b8445d14 ARM sched model: Add preload instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:52 +00:00
Arnold Schwaighofer
23cb39a3d9 ARM sched model: Add more ALU and CMP thumb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183260 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:51 +00:00
Arnold Schwaighofer
1942e3254d ARM sched model: Add more ALU and CMP thumb2 instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183259 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:49 +00:00
Arnold Schwaighofer
4c53731e5b ARM sched model: Add more ALU and CMP instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:47 +00:00
Arnold Schwaighofer
611c6e1359 ARM sched model: Add divsion, loads, branches, vfp cvt
Add some generic SchedWrites and assign resources for Swift and Cortex A9.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:46 +00:00
Arnold Schwaighofer
ede7eeae32 ARMInstrInfo: Improve isSwiftFastImmShift
An instruction with less than 3 inputs is trivially a fast immediate shift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183256 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:43 +00:00
Arnold Schwaighofer
54d63ccdb7 SubtargetEmitter fix
Don't output data if we are supposed to ignore the record.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 22:15:41 +00:00
Richard Smith
2b18526696 Fix link.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183248 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 20:42:42 +00:00
Venkatraman Govindaraju
1e06bcbd63 Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 18:33:25 +00:00
David Majnemer
5a57dbef33 IndVarSimplify: check if loop invariant expansion can trap
IndVarSimplify is willing to move divide instructions outside of their
loop bodies if they are invariant of the loop.  However, it may not be
safe to expand them if we do not know if they can trap.

Instead, check to see if it is not safe to expand the instruction and
skip the expansion.

This fixes PR16041.

Testcase by Rafael Ávila de Espíndola.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183239 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 17:51:58 +00:00
David Majnemer
35e7751af4 ARM: Fix crash in ARM backend inside of ARMConstantIslandPass
The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.

This fixes PR16215.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183238 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 17:46:15 +00:00
Bob Wilson
8240ef0410 Remove "-Wl,-seg1addr -Wl,0xE0000000" from link options.
Specifying the load address for Darwin i386 dylibs was a performance
optimization for dyld that is not relevant for x86_64 or arm. We can just
remove this now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183230 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 15:26:37 +00:00
Vincent Lejeune
98017a015b R600: Swizzle texture/export instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 15:04:53 +00:00
Vincent Lejeune
9328438329 R600: Add a test for r183108
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183228 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 15:03:35 +00:00
Rafael Espindola
babae05237 Second part of pr16069
The problem this time seems to be a thinko. We were assuming that in the CFG

A
| \
|  B
| /
C

speculating the basic block B would cause only the phi value for the B->C edge
to be speculated. That is not true, the phi's are semantically in the edges, so
if the A->B->C path is taken, any code needed for A->C is not executed and we
have to consider it too when deciding to speculate B.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183226 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 14:11:59 +00:00
Hans Wennborg
deb2e9c42f Typo: s/caes/cases/ in SimplifyCFG
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 11:22:30 +00:00
Benjamin Kramer
f102f31e15 Preserve const correctness.
GCC complains about casting away const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183216 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 09:09:15 +00:00
Vladimir Medic
164de54391 Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183215 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 08:28:53 +00:00
Alexey Samsonov
888ca964a4 [llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume that symbols with zero size are in fact large enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183213 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 07:57:38 +00:00
Bill Wendling
1c611ecdfd We are now in 3.4 land. We don't need the 3.3 releaese notes in ToT anymore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183210 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 06:12:31 +00:00
Michael Gottesman
b30718af1a IEEE-754R 5.7.2 General Operations is* operations (except for isCanonical).
Specifically the following work was done:

1. If the operation was not implemented, I implemented it.

2. If the operation was already implemented, I just moved its location
in the APFloat header into the IEEE-754R 5.7.2 section. If the name was
incorrect, I put in a comment giving the true IEEE-754R name.

Also unittests have been added for all of the functions which did not
already have a unittest.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183179 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 03:46:25 +00:00
Aaron Ballman
f3d3952a8c Silencing an MSVC warning about mixing bool and unsigned int.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183176 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 01:03:03 +00:00
Aaron Ballman
f56a6ded63 Silencing an MSVC warning about */ being found outside of a comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183175 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 01:01:56 +00:00
Shuxin Yang
45c7544339 Fix a defect in code-layout pass, improving Benchmarks/Olden/em3d/em3d by about 30%
(4.58s vs 3.2s on an oldish Mac Tower). 

  The corresponding src is excerpted bellow. The lopp accounts for about 90% of execution time.
  --------------------
    cat -n test-suite/MultiSource/Benchmarks/Olden/em3d/make_graph.c
     90 
     91         for (k=0; k<j; k++)
     92           if (other_node == cur_node->to_nodes[k]) break;

  The defective layout is sketched bellow, where the two branches need to swap.
  ------------------------------------------------------------------------
      L:
         ...
      if (cond) goto out-of-loop
      goto L

  While this code sequence is defective, I don't understand why it incurs 1/3 of 
execution time. CPU-event-profiling indicates the poor laoyout dose not increase
in br-misprediction; it dosen't increase stall cycle at all, and it dosen't 
prevent the CPU detect the loop (i.e. Loop-Stream-Detector seems to be working fine
as well)... 

   The root cause of the problem is that the layout pass calls AnalyzeBranch() 
with basic-block which is not updated to reflect its current layout.

rdar://13966341


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183174 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-04 01:00:57 +00:00
Nick Lewycky
4526d1cd4a Delete dead safety check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183167 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 23:15:20 +00:00
David Majnemer
3931bdb788 SimplifyCFG: Do not transform PHI to select if doing so would be unsafe
PR16069 is an interesting case where an incoming value to a PHI is a
trap value while also being a 'ConstantExpr'.

We do not consider this case when performing the 'HoistThenElseCodeToIf'
optimization.

Instead, make our modifications more conservative if we detect that we
cannot transform the PHI to a select.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 20:43:12 +00:00
David Majnemer
404fa7257f SimplifyCFG: Small cleanup, use ICmpInst::isEquality()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183151 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 20:39:50 +00:00
Rafael Espindola
031a179b6d Remove dead code.
Thanks to Sean Silva for noticing it!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 19:42:57 +00:00
Rafael Espindola
15e5c46e49 Update RuntimeDyldELF::findOPDEntrySection the new relocation iterators.
This was missing from r182908. I didn't noticed it at the time because the MCJIT tests were
disabled when building with cmake on ppc64 (which I fixed in r183143).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 19:37:34 +00:00
Rafael Espindola
d1100b3325 Enable mcjit tests on ppc64 when building with cmake.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183143 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 19:17:21 +00:00
Tom Stellard
e5fcc0dee4 R600/SI: Add support for work item and work group intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:18 +00:00
Tom Stellard
e7397ee81a R600/SI: Add a calling convention for compute shaders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:11 +00:00
Tom Stellard
e86f9d70ca R600/SI: Custom lower i64 sign_extend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-06-03 17:40:03 +00:00