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5 Commits

Author SHA1 Message Date
Daniel Sanders
f1ef27e6e3 [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191498 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-27 10:08:31 +00:00
Daniel Sanders
f00539cc5a [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189467 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 10:12:09 +00:00
Daniel Sanders
a65f149af6 [mips][msa] Summarize tests 
Adds a comment to the start of each test summarizing the area the test covers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189465 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-28 10:02:29 +00:00
Daniel Sanders
c5158b869b [mips][msa] Removed fcge, fcgt, fsge, fsgt 
These instructions were present in a draft spec but were removed before
publication.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188782 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-20 09:41:47 +00:00
Jack Carter
d0f99639c1 [Mips][msa] Added the simple builtins (fadd to ftq) 
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq

Patch by Daniel Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188458 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-15 13:45:36 +00:00