Commit Graph

85990 Commits

Author SHA1 Message Date
Rafael Espindola
0cead1cfef Fix the cpu name and add -verify-machineinstrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166003 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 01:13:06 +00:00
Andrew Trick
27c28cef11 misched: Added handleMove support for updating all kill flags, not just for allocatable regs.
This is a medium term workaround until we have a more robust solution
in the form of a register liveness utility for postRA passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 00:22:51 +00:00
Jakob Stoklund Olesen
feab72c20a Remove unused BitVectors from getAllocatableSet().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165999 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-16 00:05:06 +00:00
Nadav Rotem
88bcf797ab LTO also needs to initialize the TargetTransform infrastructure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165997 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 22:50:02 +00:00
Jakob Stoklund Olesen
14d1dd95c7 Remove RegisterClassInfo::isReserved() and isAllocatable().
Clients can use the equivalent functions in MRI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165990 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 22:41:03 +00:00
Michael Liao
6c0e04c823 Add __builtin_setjmp/_longjmp supprt in X86 backend
- Besides used in SjLj exception handling, __builtin_setjmp/__longjmp is also
  used as a light-weight replacement of setjmp/longjmp which are used to
  implementation continuation, user-level threading, and etc. The support added
  in this patch ONLY addresses this usage and is NOT intended to support SjLj
  exception handling as zero-cost DWARF exception handling is used by default
  in X86.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165989 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 22:39:43 +00:00
Jakob Stoklund Olesen
790047620a Remove LIS::isAllocatable() and isReserved() helpers.
All callers can simply use the corresponding MRI functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165985 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 22:14:34 +00:00
Owen Anderson
3a1c35afbd Add range-based set()/reset() to BitVector. These allow fast setting/resetting of ranges of bits, particularly useful when dealing with very large BitVector's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165984 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 22:05:27 +00:00
Jakob Stoklund Olesen
fb9ebbf236 Switch most getReservedRegs() clients to the MRI equivalent.
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 21:57:41 +00:00
Jakob Stoklund Olesen
e4f273908b Freeze the reserved registers as soon as isel is complete.
Also provide an MRI::getReservedRegs() function to access the frozen
register set, and isReserved() and isAllocatable() methods to test
individual registers.

The various implementations of TRI::getReservedRegs() are quite
complicated, and many passes need to look at the reserved register set.
This patch makes it possible for these passes to use the cached copy in
MRI, avoiding a lot of malloc traffic and repeated calculations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165982 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 21:33:06 +00:00
Jim Grosbach
64ba635209 ARM: v1i64 and v2i64 VBSL intrinsic support.
rdar://12502028

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165981 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 21:23:40 +00:00
David Blaikie
66d4b0fbf4 Add dependency on llvm-bcanalyzer from tests to the CMake build.
This fixes a CMake build break introduced by r165739.

Thanks Jan Voung for the quick suggestion/fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165978 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 21:11:46 +00:00
Bill Wendling
702cc91aa1 Move the Attributes::Builder outside of the Attributes class and into its own class named AttrBuilder. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165960 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 20:35:56 +00:00
Andrew Trick
874c0a6ec7 Check output of the misched unit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165959 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 20:33:14 +00:00
Bill Wendling
5a0eeb5a9d Add comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165958 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 19:58:25 +00:00
Rafael Espindola
32522201a8 Add a cpu to try to fix the atom builder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165956 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 19:25:43 +00:00
Chad Rosier
127f5edfd9 [ms-inline asm] If we parsed a statement and the opcode is valid, then it's an instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165955 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 19:08:18 +00:00
Rafael Espindola
3da6f0392a Add testcase for pr14088.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165954 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 19:00:10 +00:00
Andrew Trick
bb20b24224 misched tests: add a triple to speculatively fix windows builders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165952 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 18:21:08 +00:00
Rafael Espindola
10ad98bbbb Make sure we iterate over newly created instructions. Fixes pr13625. Testcase to
follow in one sec.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165951 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 18:21:07 +00:00
Andrew Trick
1e94e98b0e misched: ILP scheduler for experimental heuristics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165950 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 18:02:27 +00:00
Chad Rosier
ce353b31ae [ms-inline asm] Update the end loc for ParseIntelMemOperand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165947 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 17:26:38 +00:00
Chad Rosier
8f138d1121 [ms-inline asm] Add a few new APIs to the AsmParser class in support of MS-Style
inline assembly.  For the time being, these will be called directly by clang.
However, in the near future I expect these to be sunk back into the MC layer
and more basic APIs (e.g., getClobbers(), getConstraints(), etc.) will be called
by clang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165946 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 17:19:13 +00:00
Chad Rosier
655fa1225b [ms-inline asm] Use incoming argument rather than hard coding to false.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165945 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 16:50:34 +00:00
Jan Wen Voung
0919f22dec Fix a typo in bitcode docs, from 165814.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165944 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 16:47:58 +00:00
Micah Villmow
2c39b15073 Resubmit the changes to llvm core to update the functions to support different pointer sizes on a per address space basis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165941 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 16:24:29 +00:00
Adhemerval Zanella
f35c62bf02 PowerPC: add EmitTCEntry class for TOC creation
This patch replaces the EmitRawText by a EmitTCEntry class (specialized for
each Streamer) in PowerPC64 TOC entry creation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165940 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 15:43:14 +00:00
Kostya Serebryany
2611eeda98 [asan] fix a test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165938 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 14:30:30 +00:00
Kostya Serebryany
ee4edeccab [asan] make AddressSanitizer to be a FunctionPass instead of ModulePass. This will simplify chaining other FunctionPasses with asan. Also some minor cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165936 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 14:20:06 +00:00
Chandler Carruth
d2cd73f6a5 Update the memcpy rewriting to fully support widened int rewriting. This
includes extracting ints for copying elsewhere and inserting ints when
copying into the alloca. This should fix the CanSROA assertion coming
out of Clang's regression test suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165931 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 10:24:43 +00:00
Chandler Carruth
94fc64c42f Follow-up fix to r165928: handle memset rewriting for widened integers,
and generally clean up the memset handling. It had rotted a bit as the
other rewriting logic got polished more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165930 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 10:24:40 +00:00
Silviu Baranga
bb1078ea13 Fixed PR13938: the ARM backend was crashing because it couldn't select a VDUPLANE node with the vector input size different from the output size. This was bacause the BUILD_VECTOR lowering code didn't check that the size of the input vector was correct for using VDUPLANE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165929 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 09:41:32 +00:00
Chandler Carruth
81ff90db44 First major step toward addressing PR14059. This teaches SROA to handle
cases where we have partial integer loads and stores to an otherwise
promotable alloca to widen[1] those loads and stores to cover the entire
alloca and bitcast them into the appropriate type such that promotion
can proceed.

These partial loads and stores stem from an annoying confluence of ARM's
calling convention and ABI lowering and the FCA pre-splitting which
takes place in SROA. Clang lowers a { double, double } in-register
function argument as a [4 x i32] function argument to ensure it is
placed into integer 32-bit registers (a really unnerving implicit
contract between Clang and the ARM backend I would add). This results in
a FCA load of [4 x i32]* from the { double, double } alloca, and SROA
decomposes this into a sequence of i32 loads and stores. Inlining
proceeds, code gets folded, but at the end of the day, we still have i32
stores to the low and high halves of a double alloca. Widening these to
be i64 operations, and bitcasting them to double prior to loading or
storing allows promotion to proceed for these allocas.

I looked quite a bit changing the IR which Clang produces for this case
to be more friendly, but small changes seem unlikely to help. I think
the best representation we could use currently would be to pass 4 i32
arguments thereby avoiding any FCAs, but that would still require this
fix. It seems like it might eventually be nice to somehow encode the ABI
register selection choices outside of the parameter type system so that
the parameter can be a { double, double }, but the CC register
annotations indicate that this should be passed via 4 integer registers.

This patch does not address the second problem in PR14059, which is the
reverse: when a struct alloca is loaded as a *larger* single integer.

This patch also does not address some of the code quality issues with
the FCA-splitting. Those don't actually impede any optimizations really,
but they're on my list to clean up.

[1]: Pedantic footnote: for those concerned about memory model issues
here, this is safe. For the alloca to be promotable, it cannot escape or
have any use of its address that could allow these loads or stores to be
racing. Thus, widening is always safe.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165928 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 08:40:30 +00:00
Chandler Carruth
11cb6ba5d0 Hoist the canConvertValue predicate and the convertValue transform out
into static helper functions. They're really quite generic and are going
to be needed elsewhere shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165927 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 08:40:22 +00:00
Bill Wendling
07aae2e7d5 Add an enum for the return and function indexes into the AttrListPtr object. This gets rid of some magic numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165924 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 07:29:08 +00:00
Bill Wendling
ad4643f54b Use a ::get method to create the attribute from Attributes::AttrVals instead of a constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165923 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 06:53:28 +00:00
Bill Wendling
2c6893b568 Supply a default 'operator=' method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165922 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 06:34:18 +00:00
Bill Wendling
05cc40d20c Move the AttributesImpl header file into the VMCore directory so that it can be opaque.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165920 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 05:40:12 +00:00
Bill Wendling
cb3de0bc80 Attributes Rewrite
Convert the internal representation of the Attributes class into a pointer to an
opaque object that's uniqued by and stored in the LLVMContext object. The
Attributes class then becomes a thin wrapper around this opaque
object. Eventually, the internal representation will be expanded to include
attributes that represent code generation options, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165917 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 04:46:55 +00:00
Meador Inge
a239c2e6a7 instcombine: Migrate strcmp and strncmp optimizations
This patch migrates the strcmp and strncmp optimizations from the
simplify-libcalls pass into the instcombine library call simplifier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165915 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-15 03:47:37 +00:00
Benjamin Kramer
baf522ab5f Update CMake build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165908 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 16:06:09 +00:00
Benjamin Kramer
658c62862e Fix a typo that made ImmutableMap::getMaxElement() useless.
Add a basic unit test for ImmutableMap. Found by inspection.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165907 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 15:56:39 +00:00
Benjamin Kramer
8e13dedd41 Simplify code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165904 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 11:15:42 +00:00
Benjamin Kramer
0d05acf592 Unquadratize SetVector removal loops in DSE.
Erasing from the beginning or middle of the vector is expensive, remove_if can
do it in linear time even though it's a bit ugly without lambdas.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165903 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 10:21:31 +00:00
Bill Wendling
e82a040ee0 Remove dead methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 09:21:44 +00:00
Bill Wendling
7be7848e17 Remove operator cast method in favor of querying with the correct method.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 08:54:26 +00:00
Benjamin Kramer
fd8d62c0b4 Fix use after free when deleting attributes in a chained folding set.
Can't follow the intrusive linked list when the element is gone.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165898 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 08:48:40 +00:00
Bill Wendling
2492a38afc Don't use the new syntax just yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165897 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 08:25:35 +00:00
Bill Wendling
1feacad0ca Remove the bitwise AND operators from the Attributes class. Replace it with the equivalent from the builder class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165896 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 07:52:48 +00:00
Bill Wendling
c416795fea Remove the bitwise assignment OR operator from the Attributes class. Replace it with the equivalent from the builder class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165895 91177308-0d34-0410-b5e6-96231b3b80d8
2012-10-14 07:35:59 +00:00