Commit Graph

9 Commits

Author SHA1 Message Date
Ulrich Weigand
cf0fa9b9dd [SystemZ] Add CodeGen support for scalar f64 ops in vector registers
The z13 vector facility includes some instructions that operate only on the
high f64 in a v2f64, effectively extending the FP register set from 16
to 32 registers.  It's still better to use the old instructions if the
operands happen to fit though, since the older instructions have a shorter
encoding.

Based on a patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236524 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:28:34 +00:00
Ulrich Weigand
1a21909e98 [SystemZ] Add z13 vector facility and MC support
This patch adds support for the z13 processor type and its vector facility,
and adds MC support for all new instructions provided by that facilily.

Apart from defining the new instructions, the main changes are:

- Adding VR128, VR64 and VR32 register classes.
- Making FP64 a subclass of VR64 and FP32 a subclass of VR32.
- Adding a D(V,B) addressing mode for scatter/gather operations
- Adding 1-, 2-, and 3-bit immediate operands for some 4-bit fields.
  Until now all immediate operands have been the same width as the
  underlying field (hence the assert->return change in decode[SU]ImmOperand).

In addition, sys::getHostCPUName is extended to detect running natively
on a z13 machine.

Based on a patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-05 19:23:40 +00:00
Rafael Espindola
4a6855441c Change the default of AsmWriterClassName and isMCAsmWriter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196065 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-02 04:55:42 +00:00
Richard Sandiford
eddfaad1ef [SystemZ] Start adding z196 and zEC12 support
This first step just adds definitions for SLLK, SRLK and SRAK.
The next patch will actually make use of them during codegen.

insn-bad.s tests that some form of error is reported when using these
instructions on z10.  More work is needed to get the "instruction requires:
distinct-ops" that we'd ideally like, so I've stubbed that part out for now.
I'll come back and make it mandatory once the necessary changes are in.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186680 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-19 16:09:03 +00:00
Ulrich Weigand
1d09d56fe1 [SystemZ] Add back end
This adds the actual lib/Target/SystemZ target files necessary to
implement the SystemZ target.  Note that at this point, the target
cannot yet be built since the configure bits are missing.  Those
will be provided shortly by a follow-on patch.

This version of the patch incorporates feedback from reviews by
Chris Lattner and Anton Korobeynikov.  Thanks to all reviewers!

Patch by Richard Sandiford.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181203 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-06 16:15:19 +00:00
Dan Gohman
29074ccf6c Remove the SystemZ backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142878 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-24 23:48:32 +00:00
Anton Korobeynikov
7aa03ac827 Add bunch of FP instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76019 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 14:20:24 +00:00
Anton Korobeynikov
747052c1a5 Add z9 and z10 target processors. Mark z10-only instructions as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75977 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 14:05:00 +00:00
Anton Korobeynikov
4403b930f8 Let's start another backend :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8
2009-07-16 13:27:25 +00:00