Commit Graph

39 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
bf4699c561 Add MachineRegisterInfo::constrainRegClass and use it in MachineCSE.
This function is intended to be used when inserting a machine instruction that
trivially restricts the legal registers, like LEA requiring a GR32_NOSP
argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115875 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-06 23:54:39 +00:00
Jakob Stoklund Olesen
914f2ff9e6 Begin implementation of an inline spiller.
InlineSpiller inserts loads and spills immediately instead of deferring to
VirtRegMap. This is possible now because SlotIndexes allows instructions to be
inserted and renumbered.

This is work in progress, and is mostly a copy of TrivialSpiller so far. It
works very well for functions that don't require spilling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107227 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-29 23:58:39 +00:00
Dan Gohman
a606d955de Start TargetRegisterClass indices at 0 instead of 1, so that
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 18:13:55 +00:00
Evan Cheng
3946043a80 Avoid adding duplicate function live-in's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104560 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:33:37 +00:00
Chris Lattner
65569b8ddf constify accessor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104325 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
c66c78c684 Add reg_nodbg_iterator
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103856 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-15 02:52:58 +00:00
Dan Gohman
49b4589978 Add a utility function for conservatively clearing kill flags, and make
use of it in MachineCSE.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103726 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 19:24:00 +00:00
Jakob Stoklund Olesen
82b07dc499 Simplify the tracking of used physregs to a bulk bitor followed by a transitive
closure after allocating all blocks.

Add a few more test cases for -regalloc=fast.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103500 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 20:30:28 +00:00
Evan Cheng
2ad0fcf794 Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102554 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-28 23:08:54 +00:00
Dan Gohman
98708260f5 Move the code for emitting livein copies out of SelectionDAGISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101254 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 16:51:49 +00:00
Dan Gohman
13e73f483e Move MachineRegisterInfo's isLiveIn and isLiveOut out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101145 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 16:55:37 +00:00
Evan Cheng
1423c70b8f Add MachineRegisterInfo::hasOneUse and hasOneNonDBGUse.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97663 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-03 21:18:38 +00:00
Dale Johannesen
a65aa0f0bb Add a Debug bit to MachineOperand, for uses that
are from debug info.  Add an iterator to MachineRegisterInfo
to skip Debug operands when walking the use list.  No
functional change yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-06 02:28:32 +00:00
Dan Gohman
80f6c58981 Print "..." instead of all the uninteresting register clobbers on call
instructions. This makes CodeGen dumps significantly less noisy.

Example before:
  BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def,dead>, %D1<imp-def,dead>, %D2<imp-def,dead>, %D3<imp-def,dead>, %D4<imp-def,dead>, %D5<imp-def,dead>, %D6<imp-def,dead>, %D7<imp-def,dead>, %D16<imp-def,dead>, %D17<imp-def,dead>, %D18<imp-def,dead>, %D19<imp-def,dead>, %D20<imp-def,dead>, %D21<imp-def,dead>, %D22<imp-def,dead>, %D23<imp-def,dead>, %D24<imp-def,dead>, %D25<imp-def,dead>, %D26<imp-def,dead>, %D27<imp-def,dead>, %D28<imp-def,dead>, %D29<imp-def,dead>, %D30<imp-def,dead>, %D31<imp-def,dead>, %CPSR<imp-def,dead>, %FPSCR<imp-def,dead>

Same example after:
  BL <ga:@bar>, %R0<imp-def>, %R1<imp-def,dead>, %LR<imp-def,dead>, %CPSR<imp-def,dead>, ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86583 91177308-0d34-0410-b5e6-96231b3b80d8
2009-11-09 19:38:45 +00:00
Gabor Greif
7362ce08cb eliminate all 80-col violations that I have introduced in my recent checkins (and some others more)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80304 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-27 23:44:33 +00:00
Gabor Greif
f0891be8bd Clean up the minor mess I caused with removing iterator.h. I shall take care of 80-col violations and the FIXME later. (Thanks goodness that I live in another continent, so the monkeypox did not strike me :-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80224 91177308-0d34-0410-b5e6-96231b3b80d8
2009-08-27 06:41:46 +00:00
Evan Cheng
358dec5180 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73381 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-15 08:28:29 +00:00
Evan Cheng
90f95f88c6 Move register allocation preference (or hint) from LiveInterval to MachineRegisterInfo. This allows more passes to set them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73346 91177308-0d34-0410-b5e6-96231b3b80d8
2009-06-14 20:22:55 +00:00
Dan Gohman
33f1c68cba Move MachineRegisterInfo::setRegClass out of line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69126 91177308-0d34-0410-b5e6-96231b3b80d8
2009-04-15 01:19:35 +00:00
Dan Gohman
00ffd505d3 Add empty() methods for register def lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61890 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-07 22:28:56 +00:00
Dan Gohman
2e3e5bf427 Move createVirtualRegister out-of-line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60684 91177308-0d34-0410-b5e6-96231b3b80d8
2008-12-08 04:54:11 +00:00
Evan Cheng
11a26f3697 Add a register class -> virtual registers map.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57844 91177308-0d34-0410-b5e6-96231b3b80d8
2008-10-20 20:03:28 +00:00
Dan Gohman
6d69ba8a69 Enable rematerialization of constants using AliasAnalysis::pointsToConstantMemory,
and knowledge of PseudoSourceValues. This unfortunately isn't sufficient to allow
constants to be rematerialized in PIC mode -- the extra indirection is a
complication.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54000 91177308-0d34-0410-b5e6-96231b3b80d8
2008-07-25 00:02:30 +00:00
Evan Cheng
bdf34bc12b Minor spiller tweak to unfavor reload into load/store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-19 01:16:17 +00:00
Evan Cheng
ce049437d6 Add MachineRegisterInfo::use_empty.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52451 91177308-0d34-0410-b5e6-96231b3b80d8
2008-06-18 07:47:55 +00:00
Anton Korobeynikov
43d1fd449f For PR1338: rename include/llvm/ADT/ilist and friends to end with ".h"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51687 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-29 17:41:17 +00:00
Evan Cheng
34cd4a484e Fix more -Wshorten-64-to-32 warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50659 91177308-0d34-0410-b5e6-96231b3b80d8
2008-05-05 18:30:58 +00:00
Chris Lattner
1213d67265 update comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49010 91177308-0d34-0410-b5e6-96231b3b80d8
2008-04-01 00:54:39 +00:00
Anton Korobeynikov
ae9f3a3b7c Unbreak build with gcc 4.3: provide missed includes and silence most annoying warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47367 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-20 11:08:44 +00:00
Evan Cheng
1eb5cf9c7d Added debugging routine dumpUses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47042 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-13 02:45:38 +00:00
Dan Gohman
6f0d024a53 Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
2008-02-10 18:45:23 +00:00
Dan Gohman
1327f69d98 Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46506 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-29 11:36:12 +00:00
Chris Lattner
c637d6f452 provide def_* and use_* iterators in addition to reg_* iterators.
The first only returns definitions of a register, the second only
returns uses, the third returns both.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45803 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-10 01:01:27 +00:00
Chris Lattner
9848ced5d0 don't access element zero of an array of size zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45526 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-03 01:25:31 +00:00
Chris Lattner
e138b3dd1f switch the register iterator to act more like hte LLVM value iterator: dereferencing
it now returns the machineinstr of the use.  To get the operand, use I.getOperand().

Add a new MachineRegisterInfo::replaceRegWith, which is basically like
Value::replaceAllUsesWith.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45482 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 20:36:19 +00:00
Chris Lattner
a91a7d594f Add a trivial but handy function to efficiently return the machine
instruction that defines the specified vreg.  Crazy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45480 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 03:07:29 +00:00
Chris Lattner
6c5757e4e8 add efficient iteration support for register use/def's
within a machine function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45479 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 02:55:32 +00:00
Chris Lattner
62ed6b9ade Implement automatically updated def/use lists for all MachineInstr register
operands.  The lists are currently kept in MachineRegisterInfo, but it does
not yet provide an iterator interface to them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45477 91177308-0d34-0410-b5e6-96231b3b80d8
2008-01-01 01:12:31 +00:00
Chris Lattner
84bc5427d6 Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled.  Given this expanded name, we can start 
moving other stuff into it.  For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.

Update all the clients to match.

This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
2007-12-31 04:13:23 +00:00