Commit Graph

1863 Commits

Author SHA1 Message Date
Sean Hunt
c10a62b0d5 Allow for creation of clang DeclNodes tables.
The StmtNodes generator has been generalized to allow for the
creation of DeclNodes tables as well, and another emitter was
added for DeclContexts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-30 07:21:42 +00:00
Jakob Stoklund Olesen
7c9a6e3284 Emit TargetRegisterInfo::composeSubRegIndices().
Also verify that all subregister indices compose unambiguously.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 23:48:31 +00:00
Nate Begeman
e8f0349439 Comment out some code in prep for actual .td file checkpoint.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104927 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 02:19:08 +00:00
Eli Friedman
a4fda2c757 Fix build breakage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104912 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 01:15:28 +00:00
Nate Begeman
5ddb087f7f Add support to tablegen for auto-generating arm_neon.h from a tablegen description
of the intrinsics.  The goal is to auto-generate both support for GCC-style (vector)
and ARM-style (struct of vector) intrinsics.

This is work in progress, but will be completed soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104910 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 01:08:32 +00:00
Dan Gohman
9d2cbffed0 Simplify raw_ostream usage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104874 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 19:48:08 +00:00
Dan Gohman
098d3a41e1 Minor code simplification.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104845 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 16:25:05 +00:00
Daniel Dunbar
368a456503 AsmMatcher: Ensure classes are totally ordered, so we can std::sort them reliably.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104806 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-27 05:31:32 +00:00
Jakob Stoklund Olesen
6f0ff1d578 Check that inherited subregisters all have a direct SubRegIndex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104755 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 22:15:07 +00:00
Jakob Stoklund Olesen
160a3bf74d Add StringRef::compare_numeric and use it to sort TableGen register records.
This means that our Registers are now ordered R7, R8, R9, R10, R12, ...
Not R1, R10, R11, R12, R2, R3, ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:47:28 +00:00
Jakob Stoklund Olesen
f86a619314 Suppress emmission of empty subreg/superreg/alias sets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104741 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 21:35:55 +00:00
Jakob Stoklund Olesen
ca561ffcf3 Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 17:27:12 +00:00
Jakob Stoklund Olesen
b555609e73 Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 01:21:14 +00:00
Jakob Stoklund Olesen
6a45d681e5 Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.

CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.

It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 00:28:19 +00:00
Jakob Stoklund Olesen
76f0ad7bf5 Drop the SuperregHashTable. It is essentially the same as SubregHashTable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104650 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 23:43:18 +00:00
Jakob Stoklund Olesen
1fc8e759a7 Print symbolic SubRegIndex names on machine operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104628 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:38 +00:00
Jakob Stoklund Olesen
48d0c163fb Ignore NumberHack and give each SubRegIndex instance a unique enum value instead.
This passes lit tests, but I'll give it a go through the buildbots to smoke out
any remaining places that depend on the old SubRegIndex numbering.

Then I'll remove NumberHack entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104615 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 17:21:04 +00:00
Jakob Stoklund Olesen
33276d95ef Switch SubRegSet to using symbolic SubRegIndices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 23:03:18 +00:00
Chris Lattner
ec5a0b336a diaggroup categories should take precedence over diag-specific groups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104567 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:55:47 +00:00
Jakob Stoklund Olesen
09bc029865 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 21:46:58 +00:00
Jakob Stoklund Olesen
73ea7bf450 Add the SubRegIndex TableGen class.
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 14:48:12 +00:00
Daniel Dunbar
54ddf3d9c7 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104452 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-22 21:02:29 +00:00
Daniel Dunbar
4072886a69 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 20:20:32 +00:00
Sean Hunt
853197557c Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macro
Also rename ABSTRACT to ABSTRACT_STMT

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-18 06:22:50 +00:00
Evan Cheng
22c687b642 Added a QQQQ register file to model 4-consecutive Q registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103760 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 02:13:41 +00:00
Evan Cheng
dbf67fefea Adding a v8i64 512-bit vector type. This will be used to model ARM NEON intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 23:55:47 +00:00
Chandler Carruth
93ca7b60bf Update tablegen to generate shorts instead of chars for subgroup arrays.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103704 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-13 07:43:47 +00:00
Dan Gohman
a6cb641f48 Add initial kill flag support to FastISel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 23:54:07 +00:00
Douglas Gregor
7d9663c70b Fixes for Microsoft Visual Studio 2010, from Steven Watanabe!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103457 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-11 06:17:44 +00:00
Sean Callanan
1a8b789a4b Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:59:00 +00:00
Dan Gohman
34dcc6fadc Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 20:33:48 +00:00
Evan Cheng
b63387afc6 Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103172 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 06:36:08 +00:00
Sean Hunt
44ed2c31a5 Fix some stylistic issues with my last commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103164 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-06 05:24:38 +00:00
Shantonu Sen
d1dd5ed0ed Add newline to end of file to avoid warning
when building llvm with clang


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103084 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 13:56:46 +00:00
Sean Hunt
dc896a4118 Include the right header for toupper
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103073 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 04:31:44 +00:00
Sean Hunt
84e2f959b7 Add an emitter to handle the list of clang statement nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103071 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-05 04:13:08 +00:00
Chris Lattner
af1465b17b add the ability to associate 'category' names with clang diagnostics
and diagnostic groups.  This allows the compiler to group 
diagnostics together (e.g. "Logic Warning", 
"Format String Warning", etc) like the static analyzer does.  
This is not exposed through anything in the compiler yet.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103050 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 20:44:23 +00:00
Daniel Dunbar
4f83e73a6d MC/Matcher: Add support for over-riding the default MatchInstruction function
name (for example, to allow targets to interpose the actual MatchInstruction
function).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-04 00:33:13 +00:00
Evan Cheng
b55c8bed9d Add a pseudo instruction REG_SEQUENCE that takes a list of registers and
sub-register indices and outputs a single super register which is formed from
a consecutive sequence of registers.

This is used as register allocation / coalescing aid and it is useful to
represent instructions that output register pairs / quads. For example,
v1024, v1025 = vload <address>
where v1024 and v1025 forms a register pair.

This really should be modelled as
v1024<3>, v1025<4> = vload <address>
but it would violate SSA property before register allocation is done.

Currently we use insert_subreg to form the super register:
v1026 = implicit_def
v1027 - insert_subreg v1026, v1024, 3
v1028 = insert_subreg v1027, v1025, 4
...
      = use v1024
      = use v1028

But this adds pseudo live interval overlap between v1024 and v1025.

We can now modeled it as
v1024, v1025 = vload <address>
v1026 = REG_SEQUENCE v1024, 3, v1025, 4
...
      = use v1024
      = use v1026

After coalescing, it will be
v1026<3>, v1025<4> = vload <address>
...
      = use v1026<3>
      = use v1026


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-01 00:28:44 +00:00
Sean Callanan
a0f914b6c1 Fixes to edis that mark x86 call targets as
memory operands rather than immediate operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102217 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-23 22:17:17 +00:00
Johnny Chen
56a1afb6b0 When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 18:45:24 +00:00
Chris Lattner
acfb70f750 stop computing InstImpInputs, it is dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101881 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 06:30:25 +00:00
Chris Lattner
62bcec82b2 DAGInstruction::ImpOperands is dead after my recent tblgen work, zap it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101880 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-20 06:28:43 +00:00
Anton Korobeynikov
928eb49cae Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-18 20:31:01 +00:00
Dan Gohman
b35798347e Fix a bunch of namespace polution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101376 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-15 17:08:50 +00:00
Benjamin Kramer
be10811323 EDis: Don't include inttypes.h. We support compilers which don't provide it. It was unused anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101241 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-14 13:56:38 +00:00
Sean Callanan
9899f70a74 Fixed a nasty layering violation in the edis source
code.  It used to #include the enhanced disassembly
information for the targets it supported straight
out of lib/Target/{X86,ARM,...} but now it uses a
new interface provided by MCDisassembler, and (so
far) implemented by X86 and ARM.

Also removed hacky #define-controlled initialization
of targets in edis.  If clients only want edis to
initialize a limited set of targets, they can set
--enable-targets on the configure command line.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-13 21:21:57 +00:00
Johnny Chen
1808e4d251 If all the bit positions are not specified; do not decode the instructions.
We are bound to fail!  For proper disassembly, the well-known encoding bits
of the instruction must be fully specified.

This also removes pseudo instructions from considerations of disassembly,
which is a better design and less fragile than the name matchings.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100899 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 21:01:02 +00:00
Bob Wilson
ec80e2693a Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100892 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 20:41:18 +00:00
Johnny Chen
e0c74fb1de ARM decoder emitter should print out useful information unconditionally when it
encounters decoding conflicts, instead of wrapping it inside the DEBUG() macro. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100886 91177308-0d34-0410-b5e6-96231b3b80d8
2010-04-09 19:31:33 +00:00