Bradley Smith
a8f8d292ca
[ARM64] Add missing tlbi operands and error for extra/missing register on tlbi aliases.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205876 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:11 +00:00
Bradley Smith
3d41487f0e
[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:43:06 +00:00
Bradley Smith
4be472c874
[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205871 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:49 +00:00
Bradley Smith
fb7edfa9a5
[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205868 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:36 +00:00
Bradley Smith
a5b549e03c
[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205864 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:07 +00:00
Bradley Smith
4580af747e
[ARM64] Add missing 1Q -> 1q vector kind alias
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205863 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:42:01 +00:00
Bradley Smith
1ff9280e05
[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205862 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:58 +00:00
Bradley Smith
f5234a2c6c
[ARM64] Correctly alias LSL to UXTW for 32bit instruction variants, rather than UXTX
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205861 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-09 14:41:53 +00:00
Tim Northover
7b837d8c75
ARM64: initial backend import
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This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.
Everything will be easier with the target in-tree though, hence this
commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00
