Bradley Smith 3d41487f0e [ARM64] Rework system register parsing to overcome SPSel clash in MSR variants. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205875 91177308-0d34-0410-b5e6-96231b3b80d8

2014-04-09 14:43:06 +00:00

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advsimd.s

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aliases.s

[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.

2014-04-09 14:42:49 +00:00

arithmetic-encoding.s

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arm64-fixup.s

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basic-a64-instructions.s

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bitfield-encoding.s

[ARM64] Add WZR to isGPR32Register, since every use needs to check for this anyway.

2014-04-09 14:42:49 +00:00

branch-encoding.s

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crypto.s

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diags.s

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directive_loh.s

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elf-relocs.s

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fp-encoding.s

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large-relocs.s

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lit.local.cfg

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logical-encoding.s

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mapping-across-sections.s

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mapping-within-section.s

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memory.s

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nv-cond.s

[ARM64] Add support for NV condition code (exists only for valid assembly/disassembly, equivilant to AL)

2014-04-09 14:42:07 +00:00

separator.s

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simd-ldst.s

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small-data-fixups.s

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spsel-sysreg.s

[ARM64] Rework system register parsing to overcome SPSel clash in MSR variants.

2014-04-09 14:43:06 +00:00

system-encoding.s

[ARM64] Switch the decoder, disassembler, instprinter and asmparser over to using AArch64-style system registers, and fix up test failures discovered in the process.

2014-04-09 14:42:36 +00:00

tls-modifiers-darwin.s

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tls-relocs.s

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variable-exprs.s

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vector-lists.s

[ARM64] Add parsing for vector lists such as {v0.8b-v3.8b}

2014-04-09 14:41:58 +00:00

verbose-vector-case.s

[ARM64] Add missing 1Q -> 1q vector kind alias

2014-04-09 14:42:01 +00:00