bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
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I was trying to check the WIP file to some local repository, but ended up
checking in the llvm repository. Oops!
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set, these flags indicate the instructions source / def operands have special
register allocation requirement that are not captured in their register classes.
Post-allocation passes (e.g. post-alloc scheduler) should not change their
allocations. e.g. ARM::LDRD require the two definitions to be allocated
even / odd register pair.
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unused DECLARE instruction.
KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF
in the places where IMPLICIT_DEF is just used to alter liveness of physical
registers.
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- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
This eliminates MachineInstr's std::list member and allows the data to be
created by isel and live for the remainder of codegen, avoiding a lot of
copying and unnecessary translation. This also shrinks MemSDNode.
- Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
fields for MachineMemOperands.
- Change MemSDNode to have a MachineMemOperand member instead of its own
fields with the same information. This introduces some redundancy, but
it's more consistent with what MachineInstr will eventually want.
- Ignore alignment when searching for redundant loads for CSE, but remember
the greatest alignment.
Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.
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naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
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the MCInst path of the asmprinter. Instead, pull comment printing
out of the autogenerated asmprinter into each target that uses the
autogenerated asmprinter. This causes code duplication into each
target, but in a way that will be easier to clean up later when more
asmprinter stuff is commonized into the base AsmPrinter class.
This also fixes an xcore strangeness where it inserted two tabs
before every instruction.
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a return in one case. Instead of sprinking return handling code
throughout the asmprinter generator, just treat it like any other
normal statement.
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asm printer into the "printInstruction" routine. This
fixes a problem where the experimental asmprinter would
drop debug labels in some cases, and fixes issues on ppc/xcore
where pseudo instructions like "mr" didn't get debug locs properly.
It is annoying that this moves the call from one place into each
target, but a future set of more invasive refactorings will fix
that problem.
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inferencing. As far as I can tell, these are equivalent to the existing
MVT::fAny, iAny and vAny types, and having both of them makes it harder
to reason about and modify the type inferencing code.
The specific problem in PR4795 occurs when updating a vAny type to be fAny
or iAny, or vice versa. Both iAny and fAny include vector types -- they
intersect with the set of types represented by vAny. When merging them,
choose fAny/iAny to represent the intersection. This is not perfect, since
fAny/iAny also include scalar types, but it is good enough for TableGen's
type inferencing.
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This is conventional command-line tool behavior. -f now just means
"enable binary output on terminals".
Add a -f option to llvm-extract and llvm-link, for consistency.
Remove F_Force from raw_fd_ostream and enable overwriting and
truncating by default. Introduce an F_Excl flag to permit users to
enable a failure when the file already exists. This flag is
currently unused.
Update Makefiles and documentation accordingly.
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member out of line. ftostr is not particularly speedy,
so that method is presumably not perf sensitive.
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